Gate-all-around transistors in 2026: overview
Gate-all-around (GAA) transistors surround the semiconductor channel with a gate, giving the gate stronger electrostatic control than a FinFET’s three-sided gate. This can help control leakage and support continued logic scaling. The leading architecture uses stacked nanosheets, but its promise depends on precise channel release, gate-stack formation and source/drain integration. Heat, parasitic capacitance and interface defects remain important constraints.
Recent work focuses on making device improvements translate into circuit gains. In October 2026, Peking University researchers described a closed-loop design-technology co-optimization flow, while researchers at the University of Chinese Academy of Sciences and the Institute of Microelectronics, Chinese Academy of Sciences proposed a SiGe-channel device with trench removal and a self-aligned backside contact. A September 2026 study from the Chinese Academy of Sciences CAS and the University of Chinese Academy of Sciences demonstrated threshold-voltage modulation using TMA-regulated La-dipole engineering. Together, these efforts highlight process integration and device-to-circuit optimization as central challenges.
- 1Optimize beyond devices: Design-technology co-optimization is gaining importance because better transistor metrics do not automatically deliver faster or lower-power standard cells.
- 2Backside integration advances: Self-aligned backside contacts and backside power connections aim to improve integration, but add process-control and thermal challenges.
- 3Nanosheets still lead: Stacked nanosheets remain the dominant approach, while work on 2D and III-V channels explores alternatives with difficult contact and material-integration trade-offs.
Top organizations working on gate-all-around transistors
Ranked by Linknovate activity score · last 24 monthsThe activity score adds up the relevance of every patent, publication, grant and news item linking an organization to gate-all-around transistors. Showing 7 of 174 organizations.
| # | Organization | Approach | Signals (24 mo) | Momentum | Why it matters |
|---|---|---|---|---|---|
| 1 | 
Intel Corporation
Corporate · United States |
Stacked nanosheets | PAT 50 · PUB 9 NEWS 115 |
-50% | Recently, Intel reported a dual-contact architecture for its 18A process, aimed at lowering contact resistance and increasing drive current. Its GAA work also targets strain engineering in nanosheet channels. |
| 2 | 
Taiwan Semiconductor Manufacturing Company
Corporate · Taiwan |
Stacked nanosheets | PAT 118 · NEWS 2 | -64% | TSMC develops advanced foundry processes using GAA devices, including stacked nanosheet transistors. Its process technology enables customers to manufacture leading-edge logic chips. |
| 3 | 
TSMC
Corporate · Taiwan |
General | PAT 5 · PUB 3 NEWS 122 |
-57% | TSMC is developing advanced foundry processes that use GAA transistors for next-generation logic chips. |
| 4 | 
Applied Materials
Corporate · United States |
Stacked nanosheets | PAT 24 · PUB 2 NEWS 28 |
-26% | Applied Materials develops semiconductor fabrication equipment and process technologies relevant to GAA nanosheet formation. Its work addresses device reliability and nanosheet fabrication methods. |
| 5 | 
Samsung
Corporate · South Korea |
Stacked nanosheets | PAT 9 · PUB 6 NEWS 69 |
-53% | Samsung develops and manufactures GAA logic technology, including nanosheet-based transistors. Its work covers transistor integration and scaling for advanced semiconductor processes. |
| 6 | 
University of Chinese Academy of Sciences
Research · China |
Stacked nanosheets | PUB 36 | -29% | Recently, researchers demonstrated a SiGe-channel GAA transistor with trench removal and a self-aligned backside contact, and studied threshold-voltage control in stacked nanosheet devices. |
| 7 | 
IBM
Corporate · United States |
Stacked nanosheets | PAT 24 · PUB 2 NEWS 40 |
-35% | Recently, IBM patented a nanosheet transistor design with reverse inner spacers intended to reduce parasitic capacitance. Its GAA work also addresses source/drain contacts and device integration. |
| 8 | ··Hidden organizationCompany | Approach | PAT 00 · PUB 00 GRANTS 0 · NEWS 00 | +00% | Available to registered users. |
| 9 | ··Hidden organizationCompany | Approach | PAT 00 · PUB 00 GRANTS 0 · NEWS 00 | +00% | Available to registered users. |
| 10 | ··Hidden organizationCompany | Approach | PAT 00 · PUB 00 GRANTS 0 · NEWS 00 | +00% | Available to registered users. |
Startups to watch and leading research centers
Startups to watch 4 total
RapidusUnited StatesRapidus began prototype wafer production for a 2-nm GAA process at its IIM-1 facility, developing advanced logic manufacturing capacity in Japan.
AlsemyAlsemy develops machine-learning-based semiconductor modeling tools and has collaborated on design studies of multi-channel GAA FETs using 2D materials.- ··Hidden startupCountryAvailable to registered users, with funding and founding year.
Leading research institutions 126 total
- University of Chinese Academy of SciencesChinaRecently, researchers demonstrated a SiGe-channel GAA transistor with trench removal and a self-aligned backside contact, and studied threshold-voltage control in stacked nanosheet devices.
Chinese Academy of Sciences CASChinaRecently, researchers developed a process for rectangular, four-level stacked SiGe nanosheet GAA transistors to limit channel loss during release. They also investigated threshold-voltage modulation in stacked nanosheet devices.
Fudan UniversityChinaFudan researchers model vertical GAA transistor structures, including designs with backside contacts and engineered extension-region doping to improve scaling and balance n- and p-type performance.- ··Hidden research institutionCountryAvailable to registered users, with their key researchers.
- ··Hidden research institutionCountryAvailable to registered users, with their key researchers.
Where gate-all-around transistors innovation happens
Share of documents with at least one organization from each country.
Open the interactive map with all 174 organizationsMain technical approaches
Last 24 months| Approach | What it is | Documents | Leading organizations |
|---|---|---|---|
| Stacked nanosheets | Stacked sheets provide strong gate control and adjustable channel width, but releasing and integrating uniform sheets is demanding. | 261 |
IBM, TSMC, Intel Corporation |
| Nanowire channels | A gate wraps a narrow wire channel for strong electrostatic control, while fabrication and contact resistance can limit practical performance. | 28 |
Nanjing University, Sathyabama Institute of Science and Technology, Jeonbuk National University |
| Vertical channels | Vertical channels use device height to support dense layouts, but introduce difficult integration, contact and heat-management trade-offs. | 20 |
University of Chinese Academy of Sciences, Gaa, SNR |
| 2D semiconductor channels | Atomically thin semiconductors offer a path to very thin channels, but dependable contacts, interfaces and large-scale integration remain difficult. | 31 |
Intel Corporation, National Yang Ming Chiao Tung University, Sungkyunkwan University |
| III-V channels | III-V materials offer useful transport properties, but compound-semiconductor integration and manufacturing compatibility are persistent challenges. | 131 |
National Institute of Technology Mizoram, University of Chinese Academy of Sciences, Chinese Academy of Sciences CAS |
Emerging trends
Last 12 months vs previous 36 monthsTerms whose frequency in the last 12 months grew the most compared with the previous 36 months.
Funding and investment
Recent funding rounds
Funding data lists 2 grants totaling $287,492 since 2020. The 22 recorded funding rounds total $581.6 billion, but include broad corporate and infrastructure financing and should not be read as GAA-specific investment.
Patent landscape
Top patent holders · last 24 monthsRecent developments
Latest news, duplicates removed- Sep 2026Even small imbalances between stacked nanosheets can distort device behavior in ways that are difficult to predict from geometry alone. Gate-all-around (GAA) nanosheet transistors are revolutionizing sub-5-nm CMOS…Semiconductor Engineering
- Sep 2026Austin, Sept. 09, 2026 (GLOBE NEWSWIRE) -- According to SNS Insider, the Gate-All-Around (GAA) Transistor Market was valued at USD 685.00 Million in 2025 and is projected to reach USD 2,283.00 Million by 2035…GlobeNewswire - Research Analysis And Reports
- Sep 2026A dual contact architecture with ultra-low-resistance contacts increases drive current and enables higher frequencies at matched capacitance. With Intel 18A, Intel Foundry introduced industry-first technologies with…Semiconductor Engineering
- Aug 2026Backside power delivery and design technology co-optimization help enable the full potential of new transistor structures. By Urmimala Roy, Xi-Wei Lin, and Ravi Todi Two years ago, we introduced why the industry was…Semiconductor Engineering
- Month 20XXHidden developmentAvailable to registered users with alerts enabled.
Frequently asked questions about gate-all-around transistors
What companies are working on gate-all-around transistors?
Intel Corporation, Taiwan Semiconductor Manufacturing Company (TSMC), Samsung, IBM and Applied Materials are active in GAA-related development. Their work spans nanosheet transistor design, fabrication processes, contacts and device integration. TSMC, Intel Corporation and Samsung are chipmakers; Applied Materials develops relevant process equipment, while IBM’s work includes nanosheet structures and parasitic-capacitance reduction.
Which gate-all-around transistors startups are the most promising in 2026?
Rapidus and Alsemy are the startups identified in the GAA startup data. Rapidus is associated with stacked nanosheets and advanced logic manufacturing development. Alsemy develops machine-learning-based semiconductor modeling tools and has contributed to design studies of multi-channel GAA FETs using 2D materials. The available information does not support ranking either startup as the most promising.
Which universities and research centers lead gate-all-around transistors research?
The University of Chinese Academy of Sciences (36 documents), Chinese Academy of Sciences CAS (19) and Fudan University (17) are prominent research contributors in the listed organizations. Their work includes SiGe-channel and stacked-nanosheet devices, threshold-voltage control, and vertical GAA structures. Other active institutions include Peking University, imec and National Yang Ming Chiao Tung University.
How much funding has gate-all-around transistors received?
The funding data lists 2 grants totaling $287,492 since 2020. It also records 22 funding rounds totaling $581.6 billion, but these include broad corporate and infrastructure financing rather than only GAA research. Treat the round total as a wider semiconductor-financing signal, not as a direct measure of investment in GAA transistor development.
Who holds the most gate-all-around transistors patents?
Taiwan Semiconductor Manufacturing Company leads the listed patent holders with 118 patents. Intel Corporation has 50, while IBM and Applied Materials each have 24. These counts indicate patent activity associated with the topic; they do not establish the quality, enforceability or commercial value of each patent.
Is gate-all-around transistors patent activity growing?
Patent activity declined 56.9% over the comparison period, while publications last year increased 12.8% to 274. The data also lists 375 patents in the 24-month window. This contrast suggests that recent research output is rising even as patent activity slows, though counts alone do not show the commercial significance of individual developments.
What are the latest developments in gate-all-around transistors?
October 2026 research includes a Peking University design-technology co-optimization flow for GAA devices and standard cells, plus a proposed SiGe-channel transistor with trench removal and a self-aligned backside contact. In September 2026, researchers reported TMA-regulated La-dipole engineering for threshold-voltage modulation. These directions address circuit performance, process variation and gate-stack control.
What are the main approaches in gate-all-around transistors and how do they differ?
The main approaches are stacked nanosheets, nanowire channels, vertical channels, 2D semiconductor channels and III-V channels. Stacked nanosheets dominate current activity and allow channel-width tuning. Nanowires and vertical channels offer different geometries, while 2D and III-V materials explore alternative channel properties. Each faces distinct trade-offs in fabrication, contacts, integration or heat management.
What are the applications of gate-all-around transistors?
The application areas identified include advanced logic, mobile processors, AI and data-center computing, and on-chip memory. AI and data-center computing has 214 associated documents, while mobile processors has 87, advanced logic 84 and on-chip memory 33. These applications seek improvements in power, performance and density, with device benefits depending on successful process and circuit integration.