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Peng Z.,CAS Institute of Microelectronics | Shen H.,CAS Institute of Microelectronics | Chen H.,CAS Institute of Microelectronics | Bai Y.,CAS Institute of Microelectronics | And 6 more authors.
2016 International Forum on Wide Bandgap Semiconductors China, IFWS 2016 - Conference Proceedings | Year: 2016

The fabrication of 1200V SiC MOSFET with developed nitrided gate oxide and self-aligned channel technology are reported. Post-oxidation annealing in nitrogen-contained ambient can effectively passivate defects at the SiC/SiO2 interface which is beneficial for the mobility improvement in SiC MOSFETs. The process of nitridation begins from the conduction band and extends to the mid-band-gap gradually. Our newly developed self-aligned channel technology, where side wall and poly-silicon are used as mask instead of traditional metal mask, is efficient in shortening the MOSFET channel to half micro, which helps reduce the channel length of the device. With these two technologies mentioned above, 1200V SiC MOSFET is fabricated based on our own process line. And the current capability increases markedly after gate oxide nitridation and self-aligned channel treatment. © 2016 IEEE.


Jiang H.,Dynex Semiconductor | Jiang H.,Zhuzhou CRRC Times Electrical Co. | Jiang H.,University of Warwick | Wei J.,Hong Kong University of Science and Technology | And 5 more authors.
IEEE Electron Device Letters | Year: 2016

A silicon carbide shielded fin-shaped gate metal-oxide-semiconductor field effect transistor (SF-MOS) is proposed in this letter, which utilizes a well-grounded p-region to shield the fin-shaped trench gate. Numerical simulations by Sentaurus TCAD are carried out to study the performance of SF-MOS, and comparisons with conventional trench MOSFET and the state-of-the-art double-trench MOSFET are presented. The maximum electric field in gate oxide of the SF-MOS is effectively lowered to below 3 MV/cm, which is a widely accepted criterion for long-term gate oxide reliability. Furthermore, with the shielding effects, the gate-to-drain charge of the SF-MOS is significantly reduced, leading to lower switching loss. © 2016 IEEE.


Wei J.,Hong Kong University of Science and Technology | Jiang H.,Dynex Semiconductor | Jiang H.,Zhuzhou CRRC Times Electrical Co. | Jiang Q.,Hong Kong University of Science and Technology | Chen K.J.,Hong Kong University of Science and Technology
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2016

A novel GaN/SiC HyFET is proposed as a high-voltage power switch with low ON-resistance and enhanced switching performance. The device combines the merits of SiC vertical devices and GaN lateral HEMTs by utilizing a SiC drift region to sustain high OFF-state voltage and an enhancement-mode AlGaN/GaN heterojunction channel to reduce the channel resistance. Compared with conventional SiC MOSFETs of the same voltage rating, the HyFET exhibits a greatly reduced Ron owing to the high electron mobility in the channel, together with dramatically lower Crss and QG. Furthermore, the HyFET provides a unipolar reverse conduction diode with a smaller operating voltage and superior reverse recovery property. © 2016 IEEE.


Wei J.,Hong Kong University of Science and Technology | Zhang M.,Hong Kong Polytechnic University | Jiang H.,Dynex Semiconductor | Jiang H.,Zhuzhou CRRC Times Electrical Co. | And 2 more authors.
IEEE Electron Device Letters | Year: 2016

We propose a SiC trench/planar MOSFET (TP-MOS) which features a trench channel and a planar channel in one half-cell. Numerical simulations with Sentaurus TCAD have been carried out to study the proposed device architecture. Compared with traditional planar MOSFET (P-MOS), the TP-MOS has a much lower RON owing to the increased channel density. Unlike traditional trench MOSFET (T-MOS) which enables a higher channel density at the price of a high bottom-oxide field in the high-voltage OFF-state, the TP-MOS features bottom p-bases as in the P-MOS that protect the gate oxide from high electric field. The OFF-state oxide field in the TP-MOS is found to be even lower than the P-MOS. In addition, the TP-MOS boasts a low feedback capacitance (Crss) and gate-to-drain charge (QGD), since the coupling between the gate and the drain is suppressed by the collective effects of the top p-bases and the bottom p-bases. The QG of the TP-MOS is nearly the same as the P-MOS, and is much smaller than the T-MOS. Superior figures of merits (QG × RON and QGD × RON) are achieved in the TP-MOS. © 2016 IEEE.


Wei J.,Hong Kong University of Science and Technology | Jiang H.,Dynex Semiconductor | Jiang Q.,Zhuzhou CRRC Times Electrical Co. | Chen K.J.,Hong Kong University of Science and Technology
IEEE Transactions on Electron Devices | Year: 2016

A GaN/SiC hybrid field-effect transistor (HyFET) is proposed as a high-voltage power device that provides a high-mobility lateral AlGaN/GaN channel to reduce the channel resistance and a vertical SiC drift region to sustain the high OFF-state voltage. The performance of the HyFET is evaluated by numerical device simulations. Compared with the conventional SiC MOSFET, the HyFET exhibits a greatly reduced $R-{\mathrm{\scriptscriptstyle ON}}$ together with a low $C-{\mathrm{ GD}}$ and low gate charges. The figures of merit $Q-{\mathrm{ G}}\times R-{\mathrm{\scriptscriptstyle ON}}$ and $Q-{\mathrm{ GD}}\times R-{\mathrm{\scriptscriptstyle ON}}$ of the HyFET are dramatically improved. © 1963-2012 IEEE.


Bai Y.,CAS Institute of Microelectronics | Shen H.,CAS Institute of Microelectronics | Li C.,ZhuZhou CRRC Times Electrical CO. | Tang Y.,CAS Institute of Microelectronics | Liu X.,CAS Institute of Microelectronics
Materials Science Forum | Year: 2016

The n-p-i-n AlGaN solar-blind ultraviolet double heterojunction phototransistor (DHPT) with internal gain is proposed and optimized in this paper. The dependences of spectral responsivity and quantum gain on structure parameters of the AlGaN DHPT are simulated in detail. Then, the polarization effect of AlGaN heterojunction on the performance of AlGaN DHPT is also investigated. Results show that positive polarization charge would enhance the photoresponse of the device, whereas the negative polarization charge would reduce the photoresponse significantly. The reasons for the polarization effect on performance of AlGaN DHPT are discussed. © 2016 Trans Tech Publications, Switzerland.


Bai Y.,CAS Institute of Microelectronics | Li C.Z.,ZhuZhou CRRC Times Electrical CO. | Shen H.J.,CAS Institute of Microelectronics | Tang Y.D.,CAS Institute of Microelectronics | Liu X.Y.,CAS Institute of Microelectronics
Materials Science Forum | Year: 2016

The 4H-SiC n-p-n BJT for ultraviolet detection with high optical gain is proposed and optimized in this paper. The effect of structural parameters of 4H-SiC phototransistor on the performance of the detectors is simulated and the effect mechanism is analyzed. The simulation results show that the 4H-SiC phototransistors detect UV light with a response wavelength below 380 nm. It is suggested that the base parameters are important to the responsivity of the 4H-SiC BJT. With optimized parameters the 4H-SiC UV phototransistor exhibits peak responsivity as high as 4617 A/W corresponding to a quantum gain of 2.2×105 under the bias voltage of 5 V. © 2016 Trans Tech Publications, Switzerland.


Peng Z.Y.,CAS Institute of Microelectronics | Wang Y.Y.,Zhuzhou CRRC Times Electrical Co. | Shen H.J.,CAS Institute of Microelectronics | Bai Y.,CAS Institute of Microelectronics | And 5 more authors.
Materials Science Forum | Year: 2016

Effects of NO and forming gas annealing treatment on the interface quality and reliability of 4H-SiC MOS were systematically studied by low temperature conductance measurements in combination with time-zero dielectric breakdown and time-dependent dielectric breakdown methods. The interface trap density (Dit) showed no obvious reduction after forming gas annealing, and the values of Dit decreased significantly after combined NO and forming gas annealing treatment. The F-N barrier height, electric field to breakdown (Ebd) and charge to breakdown (Qbd) of the MOS structure increased from 2.42 eV, 10 MV/cm, 1mC/cm2 to 2.62 eV, 10.7 MV/cm, 78mC/cm2 after forming gas annealing. The values of F-N barrier height, Ebd and Qbd for MOS capacitors with combined NO and forming gas annealing treatment are 2.69 eV, 10.2 MV/cm, and 24mC/cm2. These results suggest that forming gas annealing is more effective in reliability improvement. While when considering the interface trap density, it seems that combined NO and forming gas annealing treatment is a better choice. © 2016 Trans Tech Publications, Switzerland.


Peng Z.,CAS Institute of Microelectronics | Wang Y.,Zhuzhou CRRC Times Electrical Co. | Shen H.,CAS Institute of Microelectronics | Li C.,Zhuzhou CRRC Times Electrical Co. | And 4 more authors.
Microelectronics Reliability | Year: 2015

The effects of NO and forming gas post oxidation annealing treatments on the interfacial properties and reliability of thermal oxides grown on n-type 4H-SiC (0001) Si face have been investigated in this study. The results show that forming gas annealing (FGA) treatment has limited effect on interface trap density (D it) while it results in an improvement of the insulating properties of thermal oxide with uniform high FN barrier height (2.56eV), high field-to-breakdown (10.71 MV/cm) and charge-to-breakdown (0.078 C/cm2). On the other hand, NO annealing causes a drastic reduction in D it in the entire energy level, but in the case of reliability, it is not so effective as FGA, with lower barrier height (2.52eV), field-to-breakdown (10.08 MV/cm), charge-to-breakdown (0.025 C/cm2) and worse uniformity of oxide. The combined NO&FGA treatment was also studied. It leads to a significant reduction in interface trap density further, especially in deep energy level (E C -E T ≥0.4eV). As for reliability, it brings about uniform barrier height (2.69eV), field-to-breakdown (10.15 MV/cm) and charge-to-breakdown (0.024 C/cm2). Taking interfacial properties and reliability into account, combined NO&FGA treatment is a promising POA technique for fabrication of high-quality SiC MOS devices. © 2015.


Sun Q.,Northeastern University China | Huang B.,Northeastern University China | Li D.,Zhuzhou CRRC Times Electrical Co. | Ma D.,Northeastern University China | Zhang Y.,Northeastern University China
IEEE Transactions on Industrial Informatics | Year: 2016

As system transient stability is one of the most important criterions of microgrid (MG) security operation, and the performance of an MG strongly depends on the placement of its energy storage devices (ESDs); optimal placement of ESDs for improving system transient stability is required for MGs. An MG structure preserving energy function is first developed for voltage source inverter-based MGs since the existing energy functions, based on synchronous generators and the conventional power system, are not applicable for MGs. The concept of internal potential energy of distributed energy resource is presented instead of the kinetic energy term in traditional energy function. Then, a novel approach for the optimal placement of ESDs is proposed based on MG structure preserving energy function for improving MG transient stability. Simulation and experimental results show that the proposed method can be used to find the optimal placement of ESDs and improve the system stability effectively. © 2016 IEEE.

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