Bristol, United Kingdom
Bristol, United Kingdom

XMOS is a fabless semiconductor company that develops multi-core multi-threaded processors designed to execute several real-time tasks, DSP, and control flow all at once. Wikipedia.

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News Article | May 16, 2017
Site: www.accesswire.com

UMA-8 Plug & Play Multichannel USB Microphone Array Targets DIYers, OEMs, and Researchers with Applications in Voice-Activated Control, Smart Assistants, Robotics, Conferencing, and More; The Onboard DSP Processing Supports Voice Algorithms, Including Beamforming, Noise Reduction, Acoustic Echo Cancellation, and De-Reverb to Dramatically Improve Voice Pickup HONG KONG, CHINA / ACCESSWIRE / May 16, 2017 / The UMA-8 is a high-performance yet low-cost multichannel USB microphone array built around XMOS multicore technology. Seven high-performance MEMS microphones are configured in a circular arrangement to provide high-quality voice capture for a wide range of applications. Leveraging the onboard DSP processing, the UMA-8 supports voice algorithms, including beamforming, noise reduction, acoustic echo cancellation, and de-reverb. Non-technical users can enjoy a plug & play experience, while advanced users can fine-tune all DSP parameters with a realtime Win/Mac GUI for optimum performance. The UMA-8 is a fully compliant UAC2 audio interface with driverless support for Mac/Linux and ASIO drivers for Windows. For advanced users, full control and configuration of the DSP array processing parameters are available with a real-time GUI. This can be used to fine-tune the various algorithms: acoustic echo cancellation, noise reduction, voice activation detect, and so on. With its USB API for direction of arrival, 8ch raw audio mode via USB Audio, PDM to I2S conversion, this tiny module offers a level of flexibility that engineers will certainly enjoy! Step by step application notes are now available for setup and configuration of the UMA-8 with the most common smart assistants currently available: The UMA-8 is now available at 95USD/pc on miniDSP's webshop. For more details on the user manual and product datasheet. Stay tuned for some exciting app notes!


News Article | May 16, 2017
Site: marketersmedia.com

UMA-8 is a high-performance yet low-cost multichannel USB microphone array built around XMOS multicore technology. Seven high-performance MEMS microphones are configured in a circular arrangement to provide high-quality voice capture for a wide range of applications. Leveraging the onboard DSP processing, the UMA-8 supports voice algorithms, including beamforming, noise reduction, acoustic echo cancellation, and de-reverb. Non-technical users can enjoy a plug & play experience, while advanced users can fine-tune all DSP parameters with a realtime Win/Mac GUI for optimum performance. The UMA-8 is a fully compliant UAC2 audio interface with driverless support for Mac/Linux and ASIO drivers for Windows. For advanced users, full control and configuration of the DSP array processing parameters are available with a real-time GUI. This can be used to fine-tune the various algorithms: acoustic echo cancellation, noise reduction, voice activation detect, and so on. With its USB API for direction of arrival, 8ch raw audio mode via USB Audio, PDM to I2S conversion, this tiny module offers a level of flexibility that engineers will certainly enjoy! Step by step application notes are now available for setup and configuration of the UMA-8 with the most common smart assistants currently available: The UMA-8 is now available at 95USD/pc on miniDSP's webshop. For more details on the user manual and product datasheet. Stay tuned for some exciting app notes!


Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2011.9.8 | Award Amount: 2.72M | Year: 2012

This project proposes an energy-aware system development approach covering hardware, software and the run-time environment. The central goal is to make energy usage transparent through the system layers, thus enabling optimizations both during code development and at run-time.\n\nThe project work packages will develop novel program analysis and energy modelling techniques. Tools incorporating these techniques will enable energy optimizations both during code development and at run-time, helping to promote energy efficiency to a first-class software design objective. The project will also develop a concept of optimality and a set of benchmarks allowing measurement of energy efficiency with respect to the minimal energy achievable by optimal utilization of existing hardware.\n\nLack of energy transparency in todays system development tools means that much of the potential energy saving available from power-efficient hardware is wasted. The project departs from the approach of todays systems and development tools because energy transparency is at odds with a basic principle in modern software engineering - the desire to abstract away machine-level details in high-level code in the interests of portability, understandability and software reuse. By contrast, energy transparency requires making visible the effects of energy-saving features of modern processors.\n\nThe project targets outcome (c) of Objective ICT-2011.9.8, namely to address software models and programming methodologies supporting the strive for the energetic limit (e.g. energy cost awareness or exploiting the trade-off between energy and performance/precision).


Patent
Xmos | Date: 2011-09-14

A method and corresponding tool, the method comprising: receiving as an input (a) a higher-level structure representing control flow through an executable program, the higher-level structure comprising one or more levels of parent nodes, each parent node representing internal structure comprising a group of one or more child nodes and one or more associated edges between nodes; and (b) an indication of at least one start and end instruction. The method further comprises probing the levels of the higher-level structure to extract a substructure representing a route through the program from the start to the end instruction, by selectively extracting nodes of different levels of parent to represent different regions along the route in dependence on a location of the start and end instructions relative to the levels of parent nodes; and based on the extracted substructure, estimating an execution time for the route through the program.


Patent
Xmos | Date: 2013-10-21

A processing apparatus comprising: a bus; a first processor connected to the bus and configured to communicate over the bus according to a bus protocol; a second, multithread processor; and an inter-thread interconnect based on a system of channels. The apparatus also comprises an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side for interfacing with the system of channels. The first processor is thereby operable to communicate with a designated one of said threads via the bus and a respective channel of the inter-thread interconnect.


Patent
Xmos | Date: 2010-11-18

Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address onto a respective routing direction, and a switch arranged to receive a message having a destination node address identifying a destination node. The switch comprises: means for comparing the local node address to the destination node address to identify a the most significant non-matching component; and means for routing the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching component.


Patent
Xmos | Date: 2011-09-28

A method and corresponding tool, the method comprising: generating a lower-level control flow structure representing a portion of an executable program, the lower-level control flow structure comprising a plurality of lower-level nodes representing operations occurring within the program and a plurality of directional edges representing program flow between nodes; generating a higher-level control flow structure by matching a plurality of the lower-level nodes and edges to higher-level structure nodes representing internal structure, each higher-level structure node representing a group of one or more lower-level nodes and one or more associated edges; and using the higher-level control flow structure to estimate a timing property relating to execution of the program on a processor. The higher-level structure nodes are selected exclusively from a predetermined set of structure node patterns, each pattern in the set having at most one entry point and at most one exit point.


Patent
Xmos | Date: 2010-03-12

A method and corresponding tool, the method comprising: receiving as an input (a) a higher-level structure representing control flow through an executable program, the higher-level structure comprising one or more levels of parent nodes, each parent node representing internal structure comprising a group of one or more child nodes and one or more associated edges between nodes; and (b) an indication of at least one start and end instruction. The method further comprises probing the levels of the higher-level structure to extract a substructure representing a route through the program from the start to the end instruction, by selectively extracting nodes of different levels of parent to represent different regions along the route in dependence on a location of the start and end instructions relative to the levels of parent nodes; and based on the extracted substructure, estimating an execution time for the route through the program.


Patent
Xmos | Date: 2010-03-12

A method and corresponding tool, the method comprising: generating a lower-level control flow structure representing a portion of an executable program, the lower-level control flow structure comprising a plurality of lower-level nodes representing operations occurring within the program and a plurality of directional edges representing program flow between nodes; generating a higher-level control flow structure by matching a plurality of the lower-level nodes and edges to higher-level structure nodes representing internal structure, each higher-level structure node representing a group of one or more lower-level nodes and one or more associated edges; and using the higher-level control flow structure to estimate a timing property relating to execution of the program on a processor. The higher-level structure nodes are selected exclusively from a predetermined set of structure node patterns, each pattern in the set having at most one entry point and at most one exit point.


News Article | July 21, 2014
Site: www.finsmes.com

With this investment, Dr. Hongquan Jiang from Robert Bosch will be joining the XMOS Board of Directors. The company intends to use the funds to expand customer support and accelerate new product development. Led by Nigel Toon, CEO, Xmos offers intelligent xCORE™ multicore microcontrollers that allow engineers to create the the exact hardware system needed for their application, in audio, automotive, consumer, industrial and robotics products, all in software. Customers can also download the xTIMEcomposer™ Studio development system from their website. The company has an additional development center in Chennai, India.

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