Xilinx Research Labs

San Jose, CA, United States

Xilinx Research Labs

San Jose, CA, United States

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Zhou S.,University of Southern California | Jiang W.,Xilinx Research Labs | Prasanna V.,University of Southern California
HotSDN 2014 - Proceedings of the ACM SIGCOMM 2014 Workshop on Hot Topics in Software Defined Networking | Year: 2014

This work presents a hardware-software co-design approach of an OpenFlow switch using a state-of-the-art heterogeneous System-on-chip (SoC) platform. Specifically, we implement the OpenFlow switch on a Xilinx Zynq ZC706 board. The Xilinx Zynq SoC family provides a tight coupling of field programmable gate array (FPGA) fabric and ARM processor cores, making it an attractive on-chip implementation platform for SDN switches. High-performance, yet highly-programmable, data plane processing can reside in the programmable logic (PL), while complex control software can reside in ARM processor. Our proposed architecture scales across a range of possible packet throughput rates and a range of possible flow table sizes. Post-place-and-route results show that our design targeted at Zynq can achieve a total 88 Gbps throughput for a 1K flow table which supports dynamic updates. Correct operation has been demonstrated using a ZC706 board. © 2014 Authors.

Ganegedara T.,University of Southern California | Jiang W.,Xilinx Research Labs | Prasanna V.K.,University of Southern California
IEEE Transactions on Parallel and Distributed Systems | Year: 2014

Packet classification is widely used as a core function for various applications in network infrastructure. With increasing demands in throughput, performing wire-speed packet classification has become challenging. Also the performance of today's packet classification solutions depends on the characteristics of rulesets. In this work, we propose a novel modular Bit-Vector (BV) based architecture to perform high-speed packet classification on Field Programmable Gate Array (FPGA). We introduce an algorithm named StrideBV and modularize the BV architecture to achieve better scalability than traditional BV methods. Further, we incorporate range search in our architecture to eliminate ruleset expansion caused by range-to-prefix conversion. The post place-and-route results of our implementation on a state-of-the-art FPGA show that the proposed architecture is able to operate at 100+ Gbps for minimum size packets while supporting large rulesets up to 28 K rules using only the on-chip memory resources. Our solution is ruleset-feature independent , i.e. the above performance can be guaranteed for any ruleset regardless the composition of the ruleset. © 1990-2012 IEEE.

Lotze J.,Trinity College Dublin | Fahmy S.A.,Nanyang Technological University | Noguera J.,Xilinx Research Labs | Doyle L.E.,Trinity College Dublin
IEEE Journal on Selected Areas in Communications | Year: 2011

Cognitive radio is a promising technology for fulfilling the spectrum and service requirements of future wireless communication systems. Real experimentation is a key factor for driving research forward. However, the experimentation testbeds available today are cumbersome to use, require detailed platform knowledge, and often lack high level design methods and tools. In this paper we propose a novel cognitive radio design technique, based on a high-level model which is implementation independent, supports design-time correctness checks, and clearly defines the underlying execution semantics. A radio designed using this technique can be synthesised to various real radio platforms automatically; detailed knowledge of the target platform is not required. The proposed technique therefore simplifies cognitive radio design and implementation significantly, allowing researchers to validate ideas in experiments without extensive engineering effort. One example target platform is proposed, comprising software and reconfigurable hardware. The design technique is demonstrated for this platform through the development of two realistic cognitive radio applications. © 2006 IEEE.

Gu R.,University of Maryland University College | Janneck J.W.,Xilinx Research Labs | Raulet M.,INSA Rennes | Bhattacharyya S.S.,University of Maryland University College
Journal of Signal Processing Systems | Year: 2011

Dataflow descriptions have been used in a wide range of Digital Signal Processing (DSP) applications, such as multi-media processing, and wireless communications. Among various forms of dataflow modeling, Synchronous Dataflow (SDF) is geared towards static scheduling of computational modules, which improves system performance and predictability. However, many DSP applications do not fully conform to the restrictions of SDF modeling. More general dataflow models, such as CAL (Eker and Janneck 2003), have been developed to describe dynamically-structured DSP applications. Such generalized models can express dynamically changing functionality, but lose the powerful static scheduling capabilities provided by SDF. This paper focuses on the detection of SDF-like regions in dynamic dataflow descriptions-in particular, in the generalized specification framework of CAL. This is an important step for applying static scheduling techniques within a dynamic dataflow framework. Our techniques combine the advantages of different dataflow languages and tools, including CAL (Eker and Janneck 2003), DIF (Hsu et al. 2005) and CAL2C (Roquier et al. 2008). In addition to detecting SDF-like regions, we apply existing SDF scheduling techniques to exploit the static properties of these regions within enclosing dynamic dataflow models. Furthermore, we propose an optimized approach for mapping SDF-like regions onto parallel processing platforms such as multi-core processors. © 2010 Springer Science+Business Media, LLC.

Brebner G.,Xilinx Research Labs
Conference on Optical Fiber Communication, Technical Digest Series | Year: 2015

There is a significant speed mismatch between optical transmission and the current data center. The Field Programmable Gate Array offers a flexible bridge between emergent photonic technologies and next-generation data center servers, via programmable hardware. © 2015 OSA.

Jiang W.,Xilinx Research Labs
ANCS 2013 - Proceedings of the 9th ACM/IEEE Symposium on Architectures for Networking and Communications Systems | Year: 2013

Ternary Content Addressable Memory (TCAM) is widely used in network infrastructure for various search functions. There has been a growing interest in implementing TCAM using reconfigurable hardware such as Field Programmable Gate Array (FPGA). Most of existing FPGA-based TCAM designs are based on brute-force implementations, which result in inefficient on-chip resource usage. As a result, existing designs support only a small TCAM size even with large FPGA devices. They also suffer from significant throughput degradation in implementing a large TCAM, mainly caused by deep priority encoding. This paper presents a scalable random access memory (RAM)-based TCAM architecture aiming for efficient implementation on state-of-the-art FPGAs. We give a formal study on RAM-based TCAM to unveil the ideas and the algorithms behind it. To conquer the timing challenge, we propose a modular architecture consisting of arrays of small-size RAM-based TCAM units. After decoupling the update logic from each unit, the modular architecture allows us to share each update engine among multiple units. This leads to resource saving. The capability of explicit range matching is also offered to avoid range-to-ternary conversion for search functions that require range matching. Implementation on a Xilinx Virtex 7 FPGA shows that our design can support a large TCAM of up to 2.4 Mbits while sustaining high throughput of 150 million packets per second. The resource usage scales linearly with the TCAM size. The architecture is configurable, allowing various performance trade-offs to be exploited. To the best of our knowledge, this is the first FPGA design that implements a TCAM larger than 1 Mbits. © 2013 IEEE.

Maidee P.,Xilinx Research Labs | Kaviani A.,Xilinx Research Labs
2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015 | Year: 2015

FPGA capacity has grown rapidly and emerging large applications comprise a large number of hard and soft modules. The communication among these modules requires high demand from fabric interconnect, causing routing congestion and performance degradation. This problem will be more pronounced with process scaling since the technology is not improving wire resistance. A general technique to reduce interconnect demand is sharing the wires; Network-on-Chip (NoC) is a systematic method for sharing wires. Several NoC implementations have been proposed for FPGAs in the literature, but most are designed with assumptions carried over from ASIC NoCs. In this work we examine these assumptions and modify them when necessary to customize a soft NoC for FPGAs. We developed a NoC that is tuned for FPGAs and compared it to existing NoCs in the literature. The proposed soft NoC provides 12% to 58% higher throughput per link depending on the settings. This additional throughput comes with 5% to 19% reduction in area. © 2015 IEEE.

Brebner G.,Xilinx Research Labs
2011 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference, OFC/NFOEC 2011 | Year: 2011

This paper demonstrates that Xilinx FPGA partial reconfiguration technology can yield resource and power savings in optical network elements through selective hardware modification during live operation, illustrated by two examples: data framing and EFEC calculation. © 2011 Optical Society of America.

Sutton P.D.,Trinity College Dublin | Lotze J.,Trinity College Dublin | Lahlou H.,Trinity College Dublin | Fahmy S.A.,Nanyang Technological University | And 5 more authors.
IEEE Communications Magazine | Year: 2010

Iris is a software architecture for building highly reconfigurable radio networks. It has formed the basis for a wide range of dynamic spectrum access and cognitive radio demonstration systems presented at a number of international conferences between 2007 and 2010. These systems have been developed using heterogeneous processing platforms including generalpurpose processors, field-programmable gate arrays and the Cell Broadband Engine. Focusing on runtime reconfiguration, Iris offers support for all layers of the network stack and provides a platform for the development of not only reconfigurable point-to-point radio links but complete networks of cognitive radios. This article provides an overview of Iris, presenting the unique features of the architecture and illustrating how it can be used to develop a cognitive radio testbed. © 2006 IEEE.

Brebner G.,Xilinx Research Labs
European Conference on Optical Communication, ECOC | Year: 2015

Software presents performance difficulties if it is the sole means of programmability in highspeed optical SDN and NFV. Programmable hardware, specifically the FPGA, offers an ideal cost-effective and power-efficient companion for implementing flexible SDN data planes and accelerating NFV functions. © 2015 Viajes el Corte Ingles, VECISA.

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