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Cork, Ireland

Noguera J.,Xilinx Ireland | Neuendorffer S.,Xilinx Inc. | Van Haastregt S.,Leiden University | Barba J.,University of Castilla - La Mancha | And 2 more authors.
Analog Integrated Circuits and Signal Processing

In this study we explain the implementation of a sphere detector for spatial multiplexing in broadband wireless systems using high-level synthesis (HLS) tools. These modern FPGA design tools accept C/C++ descriptions as input specifications, and automatically generate a register transfer level (RTL) description for FPGA implementation using traditional FPGA implementation tools. We have used AutoESL's AutoPilot HLS tool to implement this demanding algorithm on a Virtex-5 running at a clock frequency of 225 MHz. The obtained results show that these modern HLS tools produce Quality of Results competitive to the ones obtained using a traditional RTL design approach, while significantly abstracting the designer from the low-level FPGA implementation details. © 2011 Springer Science+Business Media, LLC. Source

Radulov G.I.,TU Eindhoven | Quinn P.J.,Xilinx Ireland | Van Roermund A.H.M.,TU Eindhoven
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

This brief presents a 7-GS/s 6-bit current-steering digital-to-analog converter (DAC) in 28-nm CMOS for VLSI System On Chip I/O embedding with an on-chip memory and clock generation circuits for wafer-sort testing. It demonstrates how Spurious Free Dynamic Range >50 dB can be maintained up to 1 GHz, while keeping the DAC footprint small -0.035 mm2. Several linearization techniques, such as current source cascodes with local biasing, thick-oxide output cascodes, bleeding currents, and 50% level of segmentation are validated for the first time at such very high frequencies. Testing is facilitated by means of integrating a digital front-end design-for-test scheme in 0.048 mm2. It uses a 5-kb 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7-GHz Current Mode Logic ring oscillator-type clock generator and a serial data interface enable simple testing of the DAC at reduced cost. © 1993-2012 IEEE. Source

Radulov G.I.,TU Eindhoven | Quinn P.J.,Xilinx Ireland | Van Roermund A.H.M.,TU Eindhoven
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

This paper presents a 3.5 GS/s 6-bit current-steering digital-to-analog converter (DAC) with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035 mm2, making it suitable to embedding in VLSI systems, e.g., field-programmable gate array (FPGA). To cope with the IC process variability, a unit element approach is generally employed. The three most significant bit (MSBs) are implemented as seven unary D/A cells and the three least significant bits (LSBs) as three binary D/A cells, using appropriately reduced number of unit elements. Furthermore, all digital gates only make use of two basic unit blocks: a buffer and a multiplexer. For testing, a memory block of 5 kb is placed on-chip, which is externally loaded in a serial way but internally read in an 8× time-interleaved way. The memory is organized around 48 clocked 104-bit shift-registers. It keeps the resulting switching disturbances signal-independent and hence avoids inducing output nonlinearity errors, even when a common power supply is shared with the DAC. This novelty allows reliable testing of the DAC core, while avoiding performance limitation risks of handling high-speed off-chip data streams. The DAC Spurious Free Dyanmic Range >40 dB bandwidth is 0.8 GHz, while the IM3 <-40 dB bandwidth exceeds 1.3 GHz. The DAC consumes 53 mW of power and the design-for-test scheme -80 mW. © 2015 IEEE. Source

Frans Y.,Xilinx Inc. | Carey D.,Xilinx Ireland | Erett M.,Xilinx Ireland | Amir-Aslanzadeh H.,Xilinx Inc. | And 10 more authors.
IEEE Journal of Solid-State Circuits

This paper describes a 0.5-16.3 Gb/s fully adaptive wireline transceiver embedded in 20 nm CMOS FPGA. The receiver utilizes bandwidth adjustable CTLE and adjustable output capacitance at the AGC to support wide range of channel loss profiles. A modified 11-tap, 1 bit speculative DFE topology provides reliable operation across all data rates. Low-latency digital CDR ensures high tracking bandwidth while still providing flexibility to support multiple protocols. The transceiver uses ring-oscillator with programmable main and cross-coupled inverter drive-strengths to wide range of operating frequency for low data-rate operation. A wide range low jitter LC-PLL utilizes feedback divider with synchronized CMOS down-counter without a prescaler to achieve a continuous divide ratio of 16-257. The clock distribution uses quadrature-error correction circuit to improve phase interpolator linearity. The transceiver achieves BER$ < 10-15 over a 28 dB loss backplane at 16.3 Gb/s and over legacy channels with 10 G-KR characteristics at 10.3125 Gb/s. The transceiver meets jitter tolerance specifications for both PCIe Gen3 at 8 Gb/s and PCIe Gen4 at 16 Gb/s in both common-clock and spread-spectrum modes. © 1966-2012 IEEE. Source

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