San Jose, CA, United States
San Jose, CA, United States

Xilinx, Inc. is an American technology company, primarily a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model.Founded in Silicon Valley in 1984, the company is headquartered in San Jose, California, with additional offices in Longmont, Colorado; Dublin, Ireland; Singapore; Hyderabad, India; Beijing, China; Shanghai, China; Brisbane, Australia and Tokyo, Japan.Major FPGA product families include Virtex , Kintex and Artix , and the retired Spartan series. Major computer software includes Xilinx ISE and Vivado Design Suite. Wikipedia.

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Patent
Xilinx Inc. | Date: 2017-06-28

An apparatus is disclosed that includes a processing sub-system (110/240) having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit (114/242) is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system (110/240) is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system (110/240), including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system (1 10/240) in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit (104/220) configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system (110/240) being disabled.


Embodiments of the invention generally provide an electronic device (100) comprising an electrical interconnect component (1 12, 122, 136) that includes an electrical trace (501 (2)). The electrical trace (501 (2)) has geometric characteristics that serve to suppress the skin effect over a large band of frequency components. More specifically, the electrical trace (501 (2)) has a thickness that is less than a skin depth for a particular chosen frequency component. By making the electrical trace (501 (2)) have a thickness that is less than the skin depth, the current flows through substantially the entire cross- sectional area of the electrical trace (501 (2)) for all frequencies up to the chosen frequency component, which reduces the effects associated with the skin effect.


To implement a circuit design on a programmable integrated circuit (IC) (100), first data are generated (202) for implementing the circuit design. Critical and non-critical portions of the circuit design with respect to Single Event Upsets (SEus) are determined (206), and second data are generated (210, 212) for programming configuration memory cells of the programmable IC to implement the circuit design. A first subset of the second data is assigned to program a first type of configuration memory cells (118) to implement the critical portion of the circuit design on a first subset of programmable logic resources (102) and a first subset of programmable interconnect resources (106) of the programmable IC. A second subset of the second data is assigned to program a second type of configuration memory cells (120) to implement the non-critical portion of the circuit design on a second subset of programmable logic resources (104) and a second subset of programmable interconnect resources (108). The second data are stored (214) in an electronically readable storage medium. The memory cells of the first type of configuration memory cells are less susceptible to SEUs than the memory cells of the second type of configuration memory cells.


Patent
Xilinx Inc. | Date: 2017-03-15

An apparatus relates generally to a repeater (210). In such an apparatus, the repeater (210) has a signal analysis and classification block (505). The signal analysis and classification block (505) includes a signal analysis block (610) and a classification block (620). The signal analysis block (610) is coupled to receive a digital signal which is a digital version of an input signal received by the repeater (210). The signal analysis block (610) is coupled to provide signal information regarding the digital signal to the classification block (620). The classification block (620) is configured to provide classification information to classify the digital signal using the signal information provided as being a waveform type of a group of waveform types.


Patent
Xilinx Inc. | Date: 2017-04-05

Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description (210, 215, 220). The second function is determined to be a data consuming function of the first function (225). Within a circuit design, a port including a local memory is automatically generated (240). The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design.


Patent
Xilinx Inc. | Date: 2017-03-22

In a transmission line via structure, a plurality of sub-structures (406) are stacked in a via (401 ) through the substrate (402) along a longitudinal axis thereof. Each of the sub-structures includes a center conductor portion (410), an outer conductor portion (412), and at least one dielectric support member (210). The center conductor portion extends along the longitudinal axis. The outer conductor portion is disposed around the center conductor portion. The dielectric support member(s) separate the outer conductor portion and the center conductor portion and provide a non-solid volume (214) between the outer conductor portion and the center conductor portion. Conductive paste (408) is disposed between the center and outer conductor portions of successive ones of the plurality of sub-structures to form an outer conductor and a center conductor.


Patent
Xilinx Inc. | Date: 2017-05-17

An apparatus relating generally to voltage conversion includes an amplifier (101) coupled to receive an input voltage (121) and a reference voltage (122). First and second converters (111, 112) are coupled to the amplifier (101) to receive a bias voltage (102). The first converter (111) includes a first transconductor (131) coupled to receive the bias voltage (102) to adjust a first tail current, and a first differential input (117P, 117M). A first inverter (141) of the first converter (111) has a first feedback device (145) coupled input-to-output to provide a first transimpedance amplifier load. The first inverter (141 ) is coupled to the first transconductor (131). The second converter (112) includes a second transconductor (132) coupled to receive the bias voltage (102) to adjust a second tail current, and a second differential input (117M, 117P). A second inverter (142) of the second converter (112) has a second feedback device (145) coupled input-to-output to provide a second transimpedance amplifier load. The second inverter (142) is coupled to the second transconductor (132).


Patent
Xilinx Inc. | Date: 2017-05-17

Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored (202) in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected (214), or translated (210) and communicated (212) to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated (226) and communicated (228) to the first bus along with the security indicator that is associated with the address translation information for the requested address.


Patent
Xilinx Inc. | Date: 2017-06-07

A system (200) for crest factor reduction (CFR) includes a peak detector (205) configured to receive an input signal (xk); a running maximum filter (210) configured to generate a scaling factor based on a window gain (Gk) and a filter length, wherein the window gain (Gk) is based on the input signal (Xk) and a threshold value (T); a window CFR gain filter (215) configured to generate a gain correction (Fk) based on the scaling factor and the filter length; a delay (225) configured to delay the input signal (Xk) to generate a delayed input signal; a multiplier (230) configured to multiply the gain correction (Fk) by the delayed input signal to obtain a peak correction value; and an adder (235) configured to determine an output signal (yk) based on the peak correction value and the delayed input signal.


Patent
Xilinx Inc. | Date: 2017-06-21

In an example, a capacitor (120) in an integrated circuit (IC) (100), includes: a first finger capacitor (104a) formed in at least one layer (M6-M8) of the IC having a first bus (202a) and a second bus (204a); a second finger capacitor (104b) formed in the at least one layer of the IC having a first bus (202b) and a second bus (204b), where a longitudinal edge (230L) of the second bus of the second finger capacitor is adjacent a longitudinal edge (228R) of the first bus of the first finger capacitor and separated by a dielectric gap (118-1 ); and a first metal segment (214-1 ) formed on a first layer (M9) above the at least one layer, the first metal segment being electrically coupled to the first bus of the first finger capacitor and increasing a width and a height of the first bus of the first finger capacitor.

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