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San Jose, CA, United States

Xilinx, Inc. is an American technology company, primarily a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model.Founded in Silicon Valley in 1984, the company is headquartered in San Jose, California, with additional offices in Longmont, Colorado; Dublin, Ireland; Singapore; Hyderabad, India; Beijing, China; Shanghai, China; Brisbane, Australia and Tokyo, Japan.Major FPGA product families include Virtex , Kintex and Artix , and the retired Spartan series. Major computer software includes Xilinx ISE and Vivado Design Suite. Wikipedia.

Trimberger S.M.,Xilinx Inc.
Proceedings of the IEEE | Year: 2015

Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 \thinspace000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than simple technology scaling. Quantitative effects of Moore's Law have driven qualitative changes in FPGA architecture, applications and tools. As a consequence, FPGAs have passed through several distinct phases of development. These phases, termed 'Ages' in this paper, are The Age of Invention, The Age of Expansion and The Age of Accumulation. This paper summarizes each and discusses their driving pressures and fundamental characteristics. The paper concludes with a vision of the upcoming Age of FPGAs. © 1963-2012 IEEE. Source

Madden L.,Xilinx Inc.
Proceedings of the International Symposium on Physical Design | Year: 2013

Since the advent of integrated circuit technology in 1958, the industry has focused primarily on monolithic integration. Unfortunately, due to physical and economic issues, the vast majority of high performance analog chips, high density memory chips, and high performance digital chips are each built on separate technologies. Therefore, in order to deliver optimum system performance, power and cost, it is desirable to integrate multiple different die, each using its own optimized technology, in a single package. This paper describes the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). The heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic solution. Mounted on a passive silicon interposer with through-silicon vias (TSVs), the heterogeneous IC stack comprises FPGA ICs with 13.1-Gb/s transceivers and dedicated analog ICs with 28-Gb/s transceivers. © 2013 ACM. Source

Duarte M.,Ecole Polytechnique Federale de Lausanne | Dick C.,Xilinx Inc. | Sabharwal A.,Rice University
IEEE Transactions on Wireless Communications | Year: 2012

We present an experiment-based characterization of passive suppression and active self-interference cancellation mechanisms in full-duplex wireless communication systems. In particular, we consider passive suppression due to antenna separation at the same node, and active cancellation in analog and/or digital domain. First, we show that the average amount of cancellation increases for active cancellation techniques as the received self-interference power increases. Our characterization of the average cancellation as a function of the self-interference power allows us to show that for a constant signal-to-interference ratio at the receiver antenna (before any active cancellation is applied), the rate of a full-duplex link increases as the self-interference power increases. Second, we show that applying digital cancellation after analog cancellation can sometimes increase the self-interference, and thus digital cancellation is more effective when applied selectively based on measured suppression values. Third, we complete our study of the impact of self-interference cancellation mechanisms by characterizing the probability distribution of the self-interference channel before and after cancellation. © 2002-2012 IEEE. Source

Engin A.E.,San Diego State University | Narasimhan S.R.,Xilinx Inc.
IEEE Transactions on Electromagnetic Compatibility | Year: 2013

This paper presents analytical formulas to extract an equivalent circuit model for coupled through silicon via (TSV) structures in a 3-D integrated circuit. We make use of a multiconductor transmission line approach to model coupled TSV structures. TSVs are embedded in a lossy silicon medium, hence they behave as metal-insulator-semiconductor (MIS) transmission lines. The models we present can accurately capture the transition between slow-wave and dielectric quasi-TEM modes, which are characteristic for MIS transmission lines, as well as the metal-oxide-semiconductor (MOS) varactor capacitance. The results agree well with 2-D quasi-static simulations and 3-D full-wave electromagnetic simulations. The derived equivalent circuit models can easily be applied in circuit simulators to analyze crosstalk behavior of TSVs in a 3-D integrated system. © 1964-2012 IEEE. Source

A semiconductor device includes a first under-bump metallization (UBM) layer disposed over a bond pad, a dielectric layer above an interconnect layer having a via exposing at least a portion of the first UBM layer. A second UBM layer is disposed above the first UBM layer and forms a UBM bucket over the via. The first UBM layer and UBM bucket are configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated.

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