Xilinx, Inc. is an American technology company, primarily a supplier of programmable logic devices. It is known for inventing the field programmable gate array and as the first semiconductor company with a fabless manufacturing model.Founded in Silicon Valley in 1984, the company is headquartered in San Jose, California, with additional offices in Longmont, Colorado; Dublin, Ireland; Singapore; Hyderabad, India; Beijing, China; Shanghai, China; Brisbane, Australia and Tokyo, Japan.Major FPGA product families include Virtex , Kintex and Artix , and the retired Spartan series. Major computer software includes Xilinx ISE and Vivado Design Suite. Wikipedia.
Xilinx Inc. | Date: 2017-05-17
Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored (202) in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected (214), or translated (210) and communicated (212) to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated (226) and communicated (228) to the first bus along with the security indicator that is associated with the address translation information for the requested address.
Xilinx Inc. | Date: 2017-06-07
A system (200) for crest factor reduction (CFR) includes a peak detector (205) configured to receive an input signal (xk); a running maximum filter (210) configured to generate a scaling factor based on a window gain (Gk) and a filter length, wherein the window gain (Gk) is based on the input signal (Xk) and a threshold value (T); a window CFR gain filter (215) configured to generate a gain correction (Fk) based on the scaling factor and the filter length; a delay (225) configured to delay the input signal (Xk) to generate a delayed input signal; a multiplier (230) configured to multiply the gain correction (Fk) by the delayed input signal to obtain a peak correction value; and an adder (235) configured to determine an output signal (yk) based on the peak correction value and the delayed input signal.
Xilinx Inc. | Date: 2017-06-21
In an example, a capacitor (120) in an integrated circuit (IC) (100), includes: a first finger capacitor (104a) formed in at least one layer (M6-M8) of the IC having a first bus (202a) and a second bus (204a); a second finger capacitor (104b) formed in the at least one layer of the IC having a first bus (202b) and a second bus (204b), where a longitudinal edge (230L) of the second bus of the second finger capacitor is adjacent a longitudinal edge (228R) of the first bus of the first finger capacitor and separated by a dielectric gap (118-1 ); and a first metal segment (214-1 ) formed on a first layer (M9) above the at least one layer, the first metal segment being electrically coupled to the first bus of the first finger capacitor and increasing a width and a height of the first bus of the first finger capacitor.
Xilinx Inc. | Date: 2017-02-08
Embodiments of the invention generally provide an electronic device (100) comprising an electrical interconnect component (1 12, 122, 136) that includes an electrical trace (501 (2)). The electrical trace (501 (2)) has geometric characteristics that serve to suppress the skin effect over a large band of frequency components. More specifically, the electrical trace (501 (2)) has a thickness that is less than a skin depth for a particular chosen frequency component. By making the electrical trace (501 (2)) have a thickness that is less than the skin depth, the current flows through substantially the entire cross- sectional area of the electrical trace (501 (2)) for all frequencies up to the chosen frequency component, which reduces the effects associated with the skin effect.
Xilinx Inc. | Date: 2017-05-24
To implement a circuit design on a programmable integrated circuit (IC) (100), first data are generated (202) for implementing the circuit design. Critical and non-critical portions of the circuit design with respect to Single Event Upsets (SEus) are determined (206), and second data are generated (210, 212) for programming configuration memory cells of the programmable IC to implement the circuit design. A first subset of the second data is assigned to program a first type of configuration memory cells (118) to implement the critical portion of the circuit design on a first subset of programmable logic resources (102) and a first subset of programmable interconnect resources (106) of the programmable IC. A second subset of the second data is assigned to program a second type of configuration memory cells (120) to implement the non-critical portion of the circuit design on a second subset of programmable logic resources (104) and a second subset of programmable interconnect resources (108). The second data are stored (214) in an electronically readable storage medium. The memory cells of the first type of configuration memory cells are less susceptible to SEUs than the memory cells of the second type of configuration memory cells.
Xilinx Inc. | Date: 2016-01-14
Methods and systems are disclosed for selecting channels for routing signals in a multi-channel switching network. In an example implementation, pairs of the signals that can be routed together over one channel in the multi-channel switching network are determined. A model graph is generated that has a respective vertex for each of the signals. The model graph also includes respective edges for the determined pairs connecting vertices corresponding to signals of the pair. A subset of the edges that includes a maximum number of disjoint edges is determined. Pairs of signals represented by the respective vertices connected by the edge are routed over a respective one of the channels. For vertices not connected to an edge in the subset, the signals represented by the vertices are routed via a respective one of the channels.
Xilinx Inc. | Date: 2017-07-19
A programmable delay circuit block (100) includes an input stage (102) having a cascade input (112) and a clock input (114), wherein the input stage (102) passes a signal received at the cascade input (112) or a signal received at the clock input (114). The programmable delay circuit block (100) further may include a delay block (104) configured to generate a delayed signal by applying a selected amount of delay to the signal passed from the input stage (102) and a pulse generator (106) configured to generate a pulse signal having a pulse width that depends upon the amount of delay. The programmable delay circuit block 100 also includes an output stage (108) having a cascade output (148) and a clock output (152). The output stage (108) is configured to pass an inverted version of the pulse signal or the delayed signal from the cascade output (148) and pass the signal received at the clock input (114), the inverted version of the pulse signal, or the delayed signal from the clock output (152).
Xilinx Inc. | Date: 2017-07-26
In a method relating generally to starting a plurality of transmitters (190), a sequence is initiated for each of the plurality of transmitters (190) having corresponding data buffers (121). Latency is set for each of the data buffers (121) responsive to execution of the sequence. The sequence includes: obtaining a read address (108) associated with a read clock signal (106) (501); obtaining a write address (109) associated with a write clock signal (105) (502); determining a difference between the read address (108) and the write address (109) (503); asserting a flag signal (113) associated with the difference (111) (504); and adjusting the read clock signal (106) to change the difference (111) to locate a change of state location for the flag signal (113) to set the latency for a data buffer (121) of the data buffers (121) (505).
Xilinx Inc. | Date: 2017-08-09
In an example implementation, an integrated circuit (IC) (102) includes: a plurality of transistors (122) disposed in a plurality of locations (120) on a die of the IC; conductors (124) coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC) (108), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC) (110), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.
Xilinx Inc. | Date: 2017-08-02
In an example, a circuit (100) to manage memory between a first and second microprocessors (102, 104) each of which is coupled to a control circuit (106), includes: first and second memory circuits (112, 1 14); and a switch circuit (110) coupled to the first and second memory circuits, and memory interfaces (210-0, 210-1) of the first and second microprocessors, the switch circuit having a mode signal as input. The switch is configured to selectively operate in one of a first mode or a second mode based on the mode signal such that, in the first mode, the switch circuit couples the first memory circuit to the memory interface of the first microprocessor and the second memory circuit to the memory interface of the second microprocessor and, in the second mode, the switch circuit selectively couples the first or second memory circuits to the memory interface of either the first or second microprocessor.