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Lou M.,Xian Micro Electronics Technique Institute | Xiao J.-Q.,Xian Micro Electronics Technique Institute | Zhang X.-Y.,Xian Micro Electronics Technique Institute | Wu L.-S.,Xian Micro Electronics Technique Institute | Guan G.-Q.,National University of Defense Technology
Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology | Year: 2016

For the problem that the traditional LRU replacement is unaware of the temporal locality in inclusive cache, a shared last-level cache (SLLC) management policy was presented for inclusive cache. With a cost-less bypass buffer stored the useless data beforehand, the policy could avoid the resource competition in SLLC between these data and highly reused data, while it still maintains the inclusion property. To further find out the least reused blocks to replace, a temporal locality detector applied was helpful to evict these blocks from SLLC as early as possible. Finally, benefited from adjustment mutually between two predictors, a unified management algorithm was proposed to bypass the useless blocks and replace the less reused blocks. Test results show that the approach reduces miss rate by 21.67% on average and improves the prediction accuracy up to 72%, while requiring less than 1% overhead of SLLC. © 2016, Beijing Institute of Technology. All right reserved. Source


Lou M.,Xian Micro Electronics Technique Institute | Xiao J.-Q.,Xian Micro Electronics Technique Institute | Zhang X.-Y.,Xian Micro Electronics Technique Institute | Wu L.-S.,Xian Micro Electronics Technique Institute | Guan G.-Q.,National University of Defense Technology
Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology | Year: 2015

To reduce the testing time and decrease the testing overhead of hardware for SoC, a high-performance SoC test structure was presented. The structure could eliminate turnaround cycle existing in traditional bi-directional test bus by reusing memory controller as test interface, while it can avoid crucial path in test channel through establishing a pipelined test sequence. Aiming at both functional and structural test requirements, the on-chip bus reused as TAM without the destructive modification could shorten the waiting cycles of test access. To balance the bandwidth between test paths and scan chains, a test wrapper independent of target core was integrated. Test results show that the approach shortens the testing time by 68%, and reduces the area overhead by 36.1%, which considerably mitigates the effects on the performance of the original chip. ©, 2015, Beijing Institute of Technology. All right reserved. Source

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