Erfurt-bindersleben, Germany
Erfurt-bindersleben, Germany

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Patent
X-FAB Semiconductor Foundries | Date: 2016-09-21

A light shield for shielding a light sensitive element in an image sensor comprising a primary plate located such as to shield the light sensitive element from incident light, the primary plate comprising at least one aperture and the or each aperture being associated with a light blocking structure, wherein the light blocking structure comprises a secondary plate and a wall; the wall is arranged between the primary plate and the secondary plate, and is configured to act as a light barrier to light passing between the primary plate and the secondary plate.


Patent
X-FAB Semiconductor Foundries | Date: 2014-11-14

Invention achieves reduced amount of terminals to control a test mode, test function and test results of a given standard for at least one wrapped core (40,100) (a core 100 surrounded by a wrapper boundary register (40) as wrapper chain). Test flexibility and speed of testing the core (100) are also improved. Suggested serial test interface comprises a state machine (210) and an instruction register (213) for wrapper-instructions, supplied through a single physical data input terminal (1a). The state machine (210) reads wrapper-instructions held by the instruction register (213) and generates on-chip wrapper control signals (30) of the given standard for the wrapper boundary register (40) of the core (100). At least one wrapper-instruction read from the Instruction Register (213) provides at least one wrapper control signal (30). The single input terminal (1a) also supplies an input test signal SDI for coupling to the wrapper boundary register (40) as on chip logical input test signal WSI. A single output terminal (1b) returns an output test signal SDO from an output WSO of the wrapper boundary register (40). Invention may apply to IEEE 1500 control signals.


Patent
X-FAB Semiconductor Foundries | Date: 2016-12-16

The invention provides a method for use in forming a semiconductor device, the semiconductor device comprising a primary area and a periphery area, the method comprising: providing a substrate on which is situated: a stack in the primary area, the stack comprising a first oxide layer on the substrate, an oxynitride layer on the first oxide layer and a second oxide layer on the oxynitride layer; and a third oxide layer in the periphery area, the method further comprising: substantially removing the second oxide layer from the primary area and the third oxide layer from the periphery area; forming a fourth oxide layer in at least the primary area by an in situ steam generation (ISSG) process; and thereafter forming a polycrystalline semiconductor layer on the fourth oxide layer without any intervening oxidation process steps. Embodiments of the invention, when applied to, for example, the manufacture of SONOS devices, have the advantages that batch-to-batch variation of the thickness of the top blocking oxide of the ONO stack is reduced or eliminated, and ONO line width variation is reduced or eliminated.


Patent
X-FAB Semiconductor Foundries | Date: 2016-11-29

An optical sensor in which photo currents generated by light in the visible and infrared wavelength ranges are to be tapped separately at pn junctions of active regions. The active regions include n- or p-doping and are formed in a p-substrate 52. The optical sensor comprises a surface-near first active region 12, and a second active region 14 subjacent to the first active region 12 and forming together with the first active region 12 a pn junction 22 that is short-circuited. A third active region 20 is subjacent to the second active region 14 and forming together with the second active region a further pn junction 23. Together with a fourth active region 24 subjacent to the second active region 20, a further pn junction 25, 29 is formed together with the third active region 20 and the substrate 52.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: NMBP-02-2016 | Award Amount: 7.43M | Year: 2017

Power electronics is the key technology to control the flow of electrical energy between source and load for a wide variety of applications from the GWs in energy transmission lines, the MWs in datacenters that power the internet to the mWs in mobile phones. Wide band gap semiconductors such as GaN use their capability to operate at higher voltages, temperatures, and switching frequencies with greater efficiencies. The GaNonCMOS project aims to bring GaN power electronic materials, devices and systems to the next level of maturity by providing the most densely integrated materials to date. This development will drive a new generation of densely integrated power electronics and pave the way toward low cost, highly reliable systems for energy intensive applications. This will be realized by integrating GaN power switches with CMOS drivers densely together using different integration schemes from the package level up to the chip level including wafer bonding between GaN on Si(111) and CMOS on Si (100) wafers. This requires the optimization of the GaN materials stack and device layout to enable fabrication of normally-off devices for such low temperature integration processes (max 400oC). In addition, new soft magnetic core materials reaching switching frequencies up to 200 Mhz with ultralow power losses will be developed. This will be assembled with new materials and methods for miniaturised packages to allow GaN devices, modules and systems to operate under maximum speed and energy efficiency. A special focus is on the long term reliability improvements over the full value chain of materials, devices, modules and systems. This is enabled by the choice of consortium partners that cover the entire value chain from universities, research centers, SMEs, large industries and vendors that incorporate the developed technology into practical systems such as datacenters, automotive, aviation and e-mobility bikes


Patent
Melexis Technologies NV and X-FAB Semiconductor Foundries | Date: 2016-04-27

A semiconductor chip (10) for measuring a magnetic field based on the Hall effect. The semiconductor chip (10) comprises an electrically conductive well (12) having a first conductivity type, in a substrate (13) having a second conductivity type. The semiconductor chip (10) comprises at least four well contacts (14) arranged at the surface of the well (12), and having the first conductivity type. The semiconductor chip (10) comprises a plurality of buffer regions (19) interleaved with the well contacts (14) and having the first conductivity type. The buffer regions (19) are highly conductive and the buffer region (19) dimensions are such that at least part of the current from a well contact (14) transits through one of its neighboring buffer regions (19).


Patent
Melexis Technologies NV and X-FAB Semiconductor Foundries | Date: 2016-06-08

A method (100) for manufacturing a system (200) in a wafer (210) for measuring an absolute and a relative pressure. In a first step (110) a shallow (220) and a deep (230) cavity are etched in the wafer (210). In a second step (120) a top wafer (510) is applied and in a third step (125) the top wafer is thinned for forming a first respectively second membrane (262, 272) over the shallow respectively deep cavity (220, 230), and for forming in the top wafer (510) first respectively second bondpads (261, 271) at the first respectively second membrane (262, 272) resulting in a first respectively second sensor (260, 270). A third step (130) back grinding the wafer (210) resulting in a opened deep cavity (230) and a still closed shallow cavity (220). The first bondpads (261) of the first sensor (260) for measuring an absolute pressure and the second bondpads (271) of the second sensor (270) a relative pressure. The etching in the first step defines the edges of the first membrane and of the second membrane in respectively the sensors formed from the shallow and the deep cavity.


Patent
X-FAB Semiconductor Foundries and Melexis Technologies NV | Date: 2015-12-02

A method for manufacturing a system in a wafer for measuring an absolute and a relative pressure includes etching a shallow and a deep cavity in the wafer. A top wafer is applied and the top wafer is thinned for forming a first respectively second membrane over the shallow respectively deep cavity, and for forming in the top wafer first respectively second bondpads at the first respectively second membrane resulting in a first respectively second sensor. Back grinding the wafer results in an opened deep cavity and a still closed shallow cavity. The first bondpads of the first sensor measure an absolute pressure and the second bondpads of the second sensor measure a relative pressure. The etching in the first step defines the edges of the first membrane and of the second membrane in respectively the sensors formed from the shallow and the deep cavity.


Patent
X-FAB Semiconductor Foundries | Date: 2016-03-28

There is provided a method for fabricating an optoelectronic semiconductor device (2,27) including a layer stack (1,26) that comprises a metallization structure (7,7) including a contact region (8,11) for electrically contacting the semiconductor device (2,27). Moreover, a dielectric layer (12) and a semiconductor layer (3) are provided. The semiconductor layer (3) comprises a functional region (6) configured as an interface for electromagnetic (visible or UV) radiation. Material in regions (17,20) above the contact region (8,11) and above the functional region (6) of the layer stack (1,26) is removed by a temporarily simultaneous etching, thereby forming two windows (24,18) for coupling the semiconductor device (2,27) to the environment, optically as well as electrically. It is an accomplishment of the invention that coupling and/or absorption losses of radiation to be analysed optically in CMOS silicon and other semiconductors is reduced at the reduced process complexity.


Patent
X-FAB Semiconductor Foundries | Date: 2015-11-04

A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously.

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