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Sarawak, Malaysia

Chu T.P.,X FAB Sarawak Sdn. Bhd.
Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA | Year: 2013

Lifetime determination is one of the reliability key tasks to have an accurate estimation of the period of time that can still survive with a certain confidence level under the specific operating conditions to perform the respective function of the applications. Various reliability tests have been designed to reveal and assess the respective wear-out degradation mechanisms. This paper presents herewith, the methodology of reliability characterization from the lifetime empirical models so as to define the corresponding Safe Operating Area (SOA) exploring to the extreme limits (in terms of operating voltages, junction temperature, area of interests or other critical dimensions, confidence bounds corresponding to failures ppm level, degradation parameters etc.). Modeling of lifetimes among these critical parameters can be done in order to find an optimized solution for a specific design. As such, a thorough reliability characterization is very important for the robust design for reliability. © 2013 IEEE. Source


Seng N.H.,X FAB Sarawak Sdn. Bhd.
ECS Transactions | Year: 2010

In high density vertical trenched power double-diffused metal oxide semiconductor (DMOS), the trench width (CD) continually shrinks as driven by the market for low cost and longer battery lifetime. Subsequently, this imposes technical challenges to keep high breakdown voltage without affecting other performances such as gate charge and on-state resistance. This paper discusses some of the technical challenges faced and suggested solutions. The various methods to improve the trench oxide uniformity and trench corner profile are also presented through experimental data. Different methods to thicken the trench bottom oxide to reduce gate-to-drain capacitance (Cgd) and eliminate the oxide weak points are introduced. This paper also reviews advanced industrial developments to increase the device switching speed as well as breakdown voltage. ©The Electrochemical Society. Source


Kho D.,X FAB Sarawak Sdn. Bhd.
2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings | Year: 2010

An experiment in base and pedestal collector implant has been conducted to study the impact and further improve the performance of a 0.6 micron silicon poly emitter bipolar transistor. It has been shown the bandwidth can be improved form 13 GHz to 15GHz with acceptable changes to the other bipolar performances. ©2010 IEEE. Source


Seng N.H.,X FAB Sarawak Sdn. Bhd. | Mei A.V.M.,X FAB Sarawak Sdn. Bhd.
RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings | Year: 2015

Hot carrier (HCI) is typical reliability test in qualifying new MOSFET device specified in JEDEC JP001 [1]. The tests are normally conducted on wafer level (WLR) using a manual probe station or automatic tester with probe card. Packaged level reliability (PLR) test system is used as well to test the MOSFET device in parallel. PLR allows higher number of samples (device under test, DUT) to be tested within a much shorter time, even applying longer stress time. The electrical connection through package units, sockets, and test boards is expected more stable than probing contact between probe pads and probe needle tips. Hence, more consistent degradation among DUT-to-DUT and accurate lifetime extrapolation can be achieved. The correlation between WLR and PLR was studied for MOSFET devices with 3.3 volt operating condition and also 12V LDMOS device. The PLR showed higher HCI degradation compared to WLR for 12V LDMOS device, whereas comparable for MOSFET. This was very low level of device self-heating effect on LDMOS from characteristic curves. However, the heat dissipation from ceramic packages took time compared to large silicon wafer on probe chuck. The stress-induced heating impact on LDMOS is discussed in this paper. © 2015 IEEE. Source


Hao Y.,X FAB Sarawak Sdn. Bhd. | Kuniss U.,X-FAB Semiconductor Foundries | Kittler G.,X-FAB Semiconductor Foundries | Hoelke A.,X FAB Sarawak Sdn. Bhd.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2013

This paper presents versatile HV lateral JFET design method on 0.18μm SOI BCD technology to achieve variable Vth(threshold voltage) and Idsat, without DIBL effect over full operating Vds range and scalable breakdown voltage capability on both N-ch and P-ch JFET. The significant advantage of a HV JFET compared to depletion MOSFET is the lower area consumption in real circuit design which due to higher Idsat values at Vgs=0V. © 2013 IEEE. Source

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