Kho E.C.T.,X FAB Sarawak Sdn Bhd |
Hoelke A.D.,X FAB Sarawak Sdn Bhd |
Pilkington S.J.,X FAB Sarawak Sdn Bhd |
Pal D.K.,X FAB Sarawak Sdn Bhd |
And 4 more authors.
IEEE Electron Device Letters | Year: 2012
This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.
Lerose D.,X-FAB Semiconductor Foundries |
Hei E.K.S.,X FAB Sarawak Sdn. Bhd. |
Ching B.C.,X FAB Sarawak Sdn. Bhd. |
Sterger M.,X FAB Dresden GmbH and Co. KG |
And 5 more authors.
Applied Optics | Year: 2013
We present a method for producing monolithically integrated complementary metal-oxide-semiconductor (CMOS) optical filters with different and customer-specific responses. The filters are constituted by a Fabry-Perot resonator formed by two Bragg mirrors separated by a patterned cavity. The filter response can be tuned by changing the geometric parameters of the patterning, and consequently the cavity effective refractive index. In this way, many different filters can be produced at once on a single chip, allowing multichanneling. The filter has been designed, produced, and characterized. The results for a chip with 24 filters are presented. © 2013 Optical Society of America.
Chu T.P.,X FAB Sarawak Sdn. Bhd.
Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA | Year: 2013
Lifetime determination is one of the reliability key tasks to have an accurate estimation of the period of time that can still survive with a certain confidence level under the specific operating conditions to perform the respective function of the applications. Various reliability tests have been designed to reveal and assess the respective wear-out degradation mechanisms. This paper presents herewith, the methodology of reliability characterization from the lifetime empirical models so as to define the corresponding Safe Operating Area (SOA) exploring to the extreme limits (in terms of operating voltages, junction temperature, area of interests or other critical dimensions, confidence bounds corresponding to failures ppm level, degradation parameters etc.). Modeling of lifetimes among these critical parameters can be done in order to find an optimized solution for a specific design. As such, a thorough reliability characterization is very important for the robust design for reliability. © 2013 IEEE.
Seng N.H.,X FAB Sarawak SDN Bhd |
Mei A.V.M.,X FAB Sarawak SDN Bhd
RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings | Year: 2015
Hot carrier (HCI) is typical reliability test in qualifying new MOSFET device specified in JEDEC JP001 . The tests are normally conducted on wafer level (WLR) using a manual probe station or automatic tester with probe card. Packaged level reliability (PLR) test system is used as well to test the MOSFET device in parallel. PLR allows higher number of samples (device under test, DUT) to be tested within a much shorter time, even applying longer stress time. The electrical connection through package units, sockets, and test boards is expected more stable than probing contact between probe pads and probe needle tips. Hence, more consistent degradation among DUT-to-DUT and accurate lifetime extrapolation can be achieved. The correlation between WLR and PLR was studied for MOSFET devices with 3.3 volt operating condition and also 12V LDMOS device. The PLR showed higher HCI degradation compared to WLR for 12V LDMOS device, whereas comparable for MOSFET. This was very low level of device self-heating effect on LDMOS from characteristic curves. However, the heat dissipation from ceramic packages took time compared to large silicon wafer on probe chuck. The stress-induced heating impact on LDMOS is discussed in this paper. © 2015 IEEE.
Hao Y.,X FAB Sarawak Sdn. Bhd. |
Kuniss U.,X-FAB Semiconductor Foundries |
Kittler G.,X-FAB Semiconductor Foundries |
Hoelke A.,X FAB Sarawak Sdn. Bhd.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2013
This paper presents versatile HV lateral JFET design method on 0.18μm SOI BCD technology to achieve variable Vth(threshold voltage) and Idsat, without DIBL effect over full operating Vds range and scalable breakdown voltage capability on both N-ch and P-ch JFET. The significant advantage of a HV JFET compared to depletion MOSFET is the lower area consumption in real circuit design which due to higher Idsat values at Vgs=0V. © 2013 IEEE.
Yien D.C.L.,X FAB Sarawak Sdn. Bhd. |
Kree I.,X FAB Sarawak Sdn. Bhd.
IEEE International Conference on Industrial Informatics (INDIN) | Year: 2010
The challenge that industry had to offer are product quality and services which meet or exceed the consumer expectation by committing faster delivery. This requires effective manufacturing controls and planning in maintaining productivity while minimizing inventory level. A good model of Material Requirements planning system is the key to optimized resources and improved inventory status, deliveries and satisfaction in planning and control. This paper reflects the methodology and improvement made in material requirements planning by integrating bill of material and related constraints into the system. © 2010 IEEE.
Seng N.H.,X FAB Sarawak Sdn. Bhd.
Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium | Year: 2010
This paper suggests an improved method to round off the concave corners of the deep trenches formed by plasma etch. The corner rounding technique, sacrificial oxidation (SACOX) before gate oxidation, has been practiced on the shallow trench isolation (STI) to improve the CMOS leakage performance. However, the direct implementation of the SACOX on the deep trenched MOSFET having less than 0.5 um trench width is insufficient to eliminate the oxide thinning at the concave corners. The experimental results including the scanning electron microscopy (SEM) images are presented to illustrate how the sharp corners vanish. The concave corners are encompassed by a smooth layer of silicon dioxide served as a gate oxide for vertical trenched MOSFET. Electrical measurement shows that the breakdown voltage was improved by eliminating the gate oxide weak spots © 2010 IEEE.
Dulin W.,X FAB Sarawak Sdn. Bhd. |
Nee O.C.,X FAB Sarawak Sdn. Bhd. |
Seng N.H.,X FAB Sarawak Sdn. Bhd.
Proceedings of the 6th Asia Symposium on Quality Electronic Design, ASQED 2015 | Year: 2015
Wafer level reliability (WLR) and package level reliability (PLR) test methods are widely used for Electromigration (EM) accelerated lifetime test. Both methods on different via structures are studied in this paper. The experimental result shows single via terminated EM structure lifetime is comparable between WLR and PLR methods based on Black's equation; while stack via terminated structure lifetime is not homogeneous between the two methods. Physical failure analysis (PFA) also shows different failure mechanisms between WLR and PLR methods on stack via terminated structure. The hypothesis is that during WLR test, large joule heating is produced at stack via area due to W-via high resistivity. The temperature even is high enough to make the aluminum between stack vias melt or burnt out. © 2015 IEEE.
Seng N.H.,X FAB Sarawak Sdn. Bhd
ECS Transactions | Year: 2010
In high density vertical trenched power double-diffused metal oxide semiconductor (DMOS), the trench width (CD) continually shrinks as driven by the market for low cost and longer battery lifetime. Subsequently, this imposes technical challenges to keep high breakdown voltage without affecting other performances such as gate charge and on-state resistance. This paper discusses some of the technical challenges faced and suggested solutions. The various methods to improve the trench oxide uniformity and trench corner profile are also presented through experimental data. Different methods to thicken the trench bottom oxide to reduce gate-to-drain capacitance (Cgd) and eliminate the oxide weak points are introduced. This paper also reviews advanced industrial developments to increase the device switching speed as well as breakdown voltage. ©The Electrochemical Society.
Kho D.,X FAB Sarawak Sdn. Bhd.
2010 International Conference on Electronic Devices, Systems and Applications, ICEDSA 2010 - Proceedings | Year: 2010
An experiment in base and pedestal collector implant has been conducted to study the impact and further improve the performance of a 0.6 micron silicon poly emitter bipolar transistor. It has been shown the bandwidth can be improved form 13 GHz to 15GHz with acceptable changes to the other bipolar performances. ©2010 IEEE.