Taichung, Taiwan

Winbond Electronics

www.winbond.com/
Taichung, Taiwan

Winbond Electronics Corporation is a Taiwan-based corporation founded in 1987 that produces semiconductors and several types of integrated circuits, most notably Dynamic RAM, Static RAM, microcontrollers, and personal computer ICs. Winbond is currently the largest brand name integrated circuit supplier in Taiwan, and one of the biggest suppliers of semiconductor solutions worldwide. Computer IC, Consumer Electronics IC and Logic Product Foundry of Winbond product lines have been spun off as Nuvoton Technology Corporation on July 1, 2008. Wikipedia.

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Patent
Winbond Electronics | Date: 2016-11-08

A NADN flash memory and a program method thereof suppressing an influence caused by FG coupling and having a high reliability are provided. The program method of the flash memory of the present invention includes a step of selecting pages of a memory array, a step of applying a programming voltage to even-numbered pages of the selected pages, a step of soft-programming odd-numbered pages of the selected pages and a step of applying the programming voltage to the odd-numbered pages after the programming of the even-numbered pages is completed.


Patent
Winbond Electronics | Date: 2017-02-08

A resistive random access memory (RRAM) element (100) including a substrate (110), a conductive layer (120), a resistive switching layer (130), a copper-containing oxide layer (140), and an electron supply layer (150) is provided. In a preferred embodiment, a CuTi/CuOx/SiNx layer structure is deposited on a Pt or TiN/Au/Ti bottom electrode overlying an oxidised Si substrate.


Patent
Winbond Electronics | Date: 2017-02-15

A resistive memory apparatus and a reading method thereof are provided. In this method, two reading pulses are applied to a resistive memory cell, such that a first reading resistance and a second reading resistance of the resistive memory cell at different temperatures are sequentially obtained. Next, a resistive state of the second reading resistance is determined according to the reading resistances and the temperatures corresponding to the reading resistances. Thereafter, a logic level of storage data of the resistive memory cell is determined according to the resistive state of the second reading resistance.


A method, a device and a non-transitory computer-readable medium for cryptographic computation are provided. The method for computation includes: receiving, in a Montgomery multiplier circuit having a predefined block size, a pair of operands A and B and a modulus M for computation of a Montgomery product of A and B mod M; specifying a number n of blocks of the predefined block size to be used in the computation; computing a blinded modulus M as a multiple of the modulus M by a random factor R, M = R*M, while selecting R so that the length of M is less than n times the block size by at least two bits; and operating the Montgomery multiplier circuit to compute and output the Montgomery product of A and B mod M.


A method for repairing of the invention includes steps as follows: storing redundant information including an address of the bad column, identification information for identifying a failure in which one of an even column or an odd column of the bad column and an address of a redundant column of a redundant memory region for repairing the bad column; determining whether a column address of a selected column is consistent with the address of the bad column based on the redundant information; when consistent, converting a column of the bad column having the failure into a column of the redundant column based on the identification information; and not converting another column of the bad column without the failure into another column of the redundant column.


Patent
Winbond Electronics | Date: 2017-01-25

A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is selected. A logic level of the logic data is determined. When the logic data is in a first logic level, where a first reading current of the corresponding resistive memory cell is greater than a first reference current, a set pulse and a reset pulse are provided to the resistive memory cell during a writing period. When the logic data is in a second logic level, where a second reading current of the resistive memory cell is smaller than a second reference current, the reset pulse is provided to the resistive memory cell during the writing period. Polarities of the reset pulse and the set pulse are opposite.


In Elliptic Curve Cryptography (ECC), one performs a great number of modular multiplications. These are usually done by Montgomery Multiplication algorithm, which needs the operands to be preprocessed (namely, converted to the Montgomery Domain), which is normally done by an equivalent of a long division. We provide a method to perform this conversion by a single Montgomery multiplication on the raw data. The method is formulated for elliptic curve points represented in Jacobian coordinates but can be extended to other representations.


Patent
Winbond Electronics | Date: 2017-09-27

An option code providing circuit includes a plurality of resistive random access memory cells and a controller. The controller determines whether to provide a control signal to operate a heavy forming operation on the resistive random access memory cells or not. Wherein, the controller performs a read operation on the resistive random access memory cells to determine a bit number of the resistive random memory cell which is heavy formed, and the option code is determined by the bit number of resistive random access memory cell which is heavy formed or a bit number of the resistive random access memory cell which is not heavy formed.


Patent
Winbond Electronics | Date: 2017-09-27

Provided is a three-dimensional resistive memory (10) with selection transistors at different levels above a substrate (100), comprising a common channel pillar (114) with gate dielectric layer (108) and gate pillar (120), first and second stacked structures (112, 104), each including alternating conductive material layers (102a) and insulating material layers (102b), and a variable resistance pillar (128) with an electrode pillar inside (132). The first and second stacked structures are respectively arranged at opposite sides of the channel pillar, and the variable resistance pillar is arranged at a side of the first stacked structure (112) opposite to the channel pillar.


A system (20), including a logic circuit (22) and delay circuitry (26) for protection from side-channel attacks by varying clock delays, is described. The logic circuit (22) is configured to perform a plurality of instances of a particular computation that is based on a plurality of inputs (I0, I1, I2, I3). The delay circuitry (26) is configured to vary a power-consumption profile of the logic circuit (22) over the plurality of instances, by applying, to the inputs (I0, I1, I2, I3), respective delays that vary over the instances, at least some of the delays varying independently from each other. The invention protects against such side-channel attacks by varying the power-consumption profile of the system (20).

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