Taichung, Taiwan

Winbond Electronics

www.winbond.com/
Taichung, Taiwan

Winbond Electronics Corporation is a Taiwan-based corporation founded in 1987 that produces semiconductors and several types of integrated circuits, most notably Dynamic RAM, Static RAM, microcontrollers, and personal computer ICs. Winbond is currently the largest brand name integrated circuit supplier in Taiwan, and one of the biggest suppliers of semiconductor solutions worldwide. Computer IC, Consumer Electronics IC and Logic Product Foundry of Winbond product lines have been spun off as Nuvoton Technology Corporation on July 1, 2008. Wikipedia.


Time filter

Source Type

Patent
Winbond Electronics | Date: 2017-05-03

Provided are a resistive memory and a method of fabricating the resistive memory. The resistive memory includes a first electrode, a second electrode, a variable resistance layer, an oxygen exchange layer, and a protection layer. The first electrode and the second electrode are arranged opposite to each other. The variable resistance layer is arranged between the first electrode and the second electrode. The oxygen exchange layer is arranged between the variable resistance layer and the second electrode. The protection layer is arranged at least on sidewalls of the oxygen exchange layer.


There is provided a computerized mechanism for vulnerability evaluation in a layout having circuitry units as interceptors, comprising receiving a layout with interceptors incorporated therein at prearranged positions, virtually inducing faults in the layout by modeling a physical phenomenon that affects timings in the layout, detecting timing violations in the layout responsive to the induced faults based on discrepancies between the timings and provided specifications thereof determining vulnerability of the layout to faults according to detected faults, and wherein the method is performed on an at least one computerized apparatus configured to perform the method.


Patent
Winbond Electronics | Date: 2016-11-08

A NADN flash memory and a program method thereof suppressing an influence caused by FG coupling and having a high reliability are provided. The program method of the flash memory of the present invention includes a step of selecting pages of a memory array, a step of applying a programming voltage to even-numbered pages of the selected pages, a step of soft-programming odd-numbered pages of the selected pages and a step of applying the programming voltage to the odd-numbered pages after the programming of the even-numbered pages is completed.


Patent
Winbond Electronics | Date: 2017-06-14

A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first bit line switch, a first resistor, a first word line switch, a second bit line switch, a second resistor, and a second word line switch. The first and second bit line switches receive a bit line signal, and are controlled by a bit line selecting signal. The fist resistor is coupled between the first bit line switch and the first word line switch. The first word line switch is controlled by a word line signal. The second resistor is coupled between the second bit line switch and the second word line switch. The second word line switch is controlled by a bit line selecting signal. When the resistive memory cell is programmed, resistances of the first and second resistors are simultaneously programmed to a high impedance or a low impedance.


Patent
Winbond Electronics | Date: 2016-02-26

A temperature detecting circuit is provided. The temperature detecting circuit includes a band gap voltage generating circuit and an offset adjusting circuit. The band gap voltage generating circuit generates a reference voltage according to a bias voltage. The band gap voltage generating circuit has a voltage dividing circuit, and the voltage dividing circuit divides the reference voltage to generate a plurality of output voltages. The offset adjusting circuit includes a current source and a resistor string. The current source provides a reference current. The resistor string receives the reference current and generates a plurality of adjusted output voltage accordingly. At least one of a current value of the reference current and a resistance of each of the resistor units is provided to be adjusted to force a voltage on an output terminal of the current source to be substantially equal to one of the reference voltage and the output voltages.


Patent
Winbond Electronics | Date: 2017-05-31

A resistive random-access memory device includes a RRAM array including a plurality of RRAM cells coupled to a source line, a controller, a bit-line decoder, and a sense circuit. Each of the RRAM cells storing a logic state and is selected by the corresponding bit line and word line. The controller selects a selected RRAM cell by a bit-line signal and a selected word line and determines the logic state according to a sense signal. The bit-line decoder couples a data bit line to the selected bit line according to a bit-line signal. The sense circuit is coupled to the data bit line and compares a memory current flowing through the selected RRAM with a reference current to generate the sense signal. The sense circuit sinks the memory current from the data bit line when operating in a reset operation and a reverse read operation. The sense circuit sources the memory current to the data bit line when operating in a set operation and a forward read operation.


Patent
Winbond Electronics | Date: 2017-07-12

The invention provides a resistive memory apparatus including at least one first resistive memory cell, a first bit line selecting switch, a first source line selecting switch, a first pull down switch and a second pull down switch. The first bit line selecting switch is coupled between a first bit line and a sense amplifier. The first source line selecting switch is coupled between a source line and the sense amplifier. The first and second pull down switches are respectively coupled to the bit line and source line. When a reading operation is operated, on or off statuses of the first bit line selecting switch and the second pull down switch are the same, on or off statuses of the first source line selecting switch and the first pull down switch are the same, and on or off statuses of the first and second pull down switches are complementary.


Patent
Winbond Electronics | Date: 2016-11-14

A NADN flash memory suppresses an influence caused by FG coupling and has high reliability. The flash memory of the invention includes: a memory array formed with a plurality of NAND strings; a row selection unit selecting rows of the memory array; and a bit line selection circuit (200) selecting even-numbered pages or odd-numbered pages of the selected row. The even-numbered pages (BL0, BL1, BL4, BL5) include a plurality of pairs of adjacent bit line pairs, the odd-numbered pages (BL2, BL3, BL6, BL7) include a plurality of pairs of adjacent bit line pairs, and the bit lines of the even-numbered page and the bit lines of the odd-numbered page are arranged alternately.


Patent
Winbond Electronics | Date: 2017-08-09

A non-volatile semiconductor memory device is provided. A determination circuit 200 used to determine the suspectedly qualified is connected with a plurality of page buffer/sensing circuits 170 via wirings PB_UP, PB_MG, PB_DIS. The page buffer/sensing circuit 170 includes a transistor Q2 in which a reference current Iref flows through a transistor Q1 when the programming verification is unqualified. The determination circuit 200 includes a comparator CMP, a voltage of the wiring PB_UP is supplied to one of input terminals of the comparator CMP, and a reference voltage Vref is supplied to another one of the input terminals. The reference voltage Vref is generated by a reference current (Iref*N) whose amount is corresponding to an unqualified bit number (N) which is determined to be suspectedly qualified.


An electronic circuit with protection against eavesdropping by power analysis is provided. The electronic circuit includes: a storage element for storing a set of bits; a logic unit for processing the stored set of bits and providing a next state set of bits after two or more cycles, wherein in a first cycle, some of the stored set of bits are provided to the logic unit correctly and some are replaced by random values and in a last cycle, all of the stored set of bits are provided to the logic unit correctly; and a random bit generator that generates a random bit for each bit of the stored set of bits to determine which bits of the stored set of bits are to be provided correctly and which bits are to be replaced in each cycle.

Loading Winbond Electronics collaborators
Loading Winbond Electronics collaborators