Taichung, Taiwan
Taichung, Taiwan

Winbond Electronics Corporation is a Taiwan-based corporation founded in 1987 that produces semiconductors and several types of integrated circuits, most notably Dynamic RAM, Static RAM, microcontrollers, and personal computer ICs. Winbond is currently the largest brand name integrated circuit supplier in Taiwan, and one of the biggest suppliers of semiconductor solutions worldwide. Computer IC, Consumer Electronics IC and Logic Product Foundry of Winbond product lines have been spun off as Nuvoton Technology Corporation on July 1, 2008. Wikipedia.


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Patent
Winbond Electronics | Date: 2016-04-01

A writing method for a resistive memory apparatus is provided. In the method, logic data is received, and a corresponding selection memory cell is selected. A logic level of the logic data is determined. When the logic data is at a first logic level, a RESET pulse is provided to the selection memory cell and then a SET pulse smaller than a reference write current and having a near-rectangular pulse width is provided to the selection memory cell during a writing period. When the logic data is at a second logic level, the RESET pulse is provided to the selection memory cell and then a SET pulse larger than the reference write current and having the near-rectangular pulse width is provided to the selection memory cell during the writing period.


Patent
Winbond Electronics | Date: 2016-08-16

A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).


Patent
Winbond Electronics | Date: 2016-01-06

A method for estimating stress of an electronic component. An electronic component including first and second elements and conductive bumps is provided. Each conductive bump has two surfaces connected to the first and second elements respectively. Two adjacent conductive bumps have a pitch therebetween. The conductive bumps includes a first conductive bump and second conductive bumps. A stress value of the first conductive bump related to a testing parameter is calculated. A stress value of each second conductive bump related to the testing parameter is calculated according to a first calculating formula. The first calculating formula is _(2 )is the stress of each second conductive bump, L is a beeline distance between each second conductive bump and the first conductive bump, D is an average value of the pitches of the conductive bumps, r is a radius of each surface, and _(1 )is the stress value of the first conductive bump.


A low density parity check (LDPC) decoding method and a decoding apparatus are provided. The method includes following steps. Based on M edges of a Tanner graph related to a parity check matrix, each of the edges is associated with one of a plurality of threads, such that each of the threads is corresponding to one of a plurality of edge identifies. When executing one of the threads, data in a shared memory is accessed according to the edge identifier of the one of the threads, so as to update a plurality of passing massages respectively corresponding to the edges in the shared memory. Thereby, high computation parallelism and fully-coalesced data accesses can be achieved.


Patent
Winbond Electronics | Date: 2016-06-14

An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits.


Patent
Winbond Electronics | Date: 2016-06-23

A memory-programming device includes a voltage generator, a resistive random-access memory, a current detector, and a controller. The voltage generator is configured to generate a program voltage. The resistive random-access memory receives the program voltage to generate a program current. The current detector detects the program current. The controller executes a program procedure. The program procedure includes: gradually ramping up the program voltage by the voltage generator and detecting the program current by the current detector; discovering the maximum of the program current to be a reference current; continuing to ramp up the program voltage by the voltage generator and determining whether the program current detected by the current detector is not less than the reference current; controlling the voltage generator to stop generating the program voltage when the program current is not less than the reference current.


A method for repairing of the invention includes steps as follows: storing redundant information including an address of the bad column, identification information for identifying a failure in which one of an even column or an odd column of the bad column and an address of a redundant column of a redundant memory region for repairing the bad column; determining whether a column address of a selected column is consistent with the address of the bad column based on the redundant information; when consistent, converting a column of the bad column having the failure into a column of the redundant column based on the identification information; and not converting another column of the bad column without the failure into another column of the redundant column.


A method, a device and a non-transitory computer-readable medium for cryptographic computation are provided. The method for computation includes: receiving, in a Montgomery multiplier circuit having a predefined block size, a pair of operands A and B and a modulus M for computation of a Montgomery product of A and B mod M; specifying a number n of blocks of the predefined block size to be used in the computation; computing a blinded modulus M as a multiple of the modulus M by a random factor R, M=R*M, while selecting R so that the length of M is less than n times the block size by at least two bits; and operating the Montgomery multiplier circuit to compute and output the Montgomery product of A and B mod M.


In Elliptic Curve Cryptography (ECC), one performs a great number of modular multiplications. These are usually done by Montgomery Multiplication algorithm, which needs the operands to be preprocessed (namely, converted to the Montgomery Domain), which is normally done by an equivalent of a long division. We provide a method to perform this conversion by a single Montgomery multiplication on the raw data. The method is formulated for elliptic curve points represented in Jacobian coordinates but can be extended to other representations.


Patent
Winbond Electronics | Date: 2016-01-06

A semiconductor memory apparatus and a data processing method are provided. The semiconductor memory apparatus gives consideration to partial page programming and data scrambling, and improves the reliability. In the flash memory of the present invention, when data is programmed to a page n times consecutively, identification information and program information are generated. A scrambled data, the location information and the flag information are programmed to a selected page in a memory array. The location information indicates a storage location for a data scrambling in the page selected based on an input address information. The flag information is used to identify a storage region specified by the location information is programed.

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