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Patent
WIN Semiconductors Corporation | Date: 2016-03-15

A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.


Patent
WIN Semiconductors Corporation | Date: 2016-12-06

The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.


Patent
WIN Semiconductors Corporation | Date: 2015-05-27

A compound semiconductor integrated circuit with three-dimensionally formed components, such as three-dimensionally formed bond pads or inductors, positioned above an electronic device. The dielectric layer inserted between the electronic device and the bond pads or inductors thereon has a thickness between 10 to 30 microns, so that it can effectively mitigate the effect of the structure on the device performance. A SiN protection layer can be disposed to cover the electronic devices to prevent contamination from the bond pad or inductor material to the electronic device, and therefore the lower cost copper can be used as the bond pad and inductor material. The three-dimensional bond pad can be used in wire bonding or bump bonding technology.


Patent
WIN Semiconductors Corporation | Date: 2015-10-14

A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.


Patent
WIN Semiconductors Corporation | Date: 2015-09-22

A biasing circuitry is disclosed. The biasing circuitry includes a biasing module, electrically connected to a power amplifier; and a control series, having an end electrically connected to a positive voltage, and another end electrically connected to the biasing module. The control series includes a switch unit, controlled by a control voltage to be on or off; and a voltage-drop unit, connected to the switch unit in series. The voltage-drop unit is configured to adjust a bias point of the power amplifier.


Patent
WIN Semiconductors Corporation | Date: 2015-09-22

A package structure is disclosed. The package structure includes at least a lead, for delivering at least a signal; at least a routing layer, connected to the at least a lead, where at least a first hole is formed through the at least a routing layer; a die, disposed on the at least a routing layer, where at least a second hole is formed through the die, and the die generates or receives the at least a signal; and a molding cap, for covering the at least a routing layer and the die; where the at least a signal is delivered through the at least a first hole and the at least a second hole.


Patent
WIN SEMICONDUCTORS Corporation | Date: 2016-04-29

A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.


Patent
WIN Semiconductors Corporation | Date: 2015-10-14

A low noise amplifier (LNA) has been disclosed for the noise and linearity performance improvement. The LNA includes an amplifying transistor and an auxiliary transistor. The amplifying transistor includes a first terminal for receiving an input signal of the LNA, a second terminal for outputting an output signal of the LNA, and a third terminal. The auxiliary transistor has a first terminal, a second terminal coupled to the second terminal of the amplifying transistor, and a third terminal electrically connected to the first terminal of the amplifying transistor.


An improved structure of backside copper metallization for semiconductor devices and a fabrication method thereof, wherein the improved structure comprises sequentially from top to bottom an active layer, a substrate, a backside metal seed layer, a high-temperature sustaining buffer layer, a backside metal layer and at least one oxidation resistant layer, wherein the backside metal seed layer contains Pd and P, the high-temperature sustaining buffer layer is made of Ni, Ag or Ni alloys, and the backside metal layer is made of Cu. The semiconductor chip using the structure provided by the present invention can sustain high-temperature operations.


Patent
WIN Semiconductors Corporation | Date: 2015-04-21

A heterojunction bipolar transistor, comprising an elongated base mesa, an elongated base electrode, two elongated emitters, an elongated collector, and two elongated collector electrodes. The elongated base electrode is formed on the base mesa along the long axis of the base mesa, and the base electrode has a base via hole at or near the center of the base electrode. The two elongated emitter are formed on the base mesa respectively at two opposite sides of the base electrode, and each of two emitters has an elongated emitter electrode formed on the emitter. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.

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