WIN Semiconductors Corporation

Taoyuan, Taiwan

WIN Semiconductors Corporation

Taoyuan, Taiwan
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Patent
WIN Semiconductors Corporation | Date: 2017-03-30

A chip stack having a protection structure for semiconductor device package comprises a first chip and a second chip stacked with each other. A first surface of the first chip and a second surface of the second chip are facing to each other. At least one metal pillar is formed on at least one of the first surface and the second surface and connected with the other. At least one protection ring is formed on at least one of the first surface and the second surface and having a first gap with the other. At least one electrical device is formed on at least one of the first surface and the second surface and is located inside at least one of the at least one protection ring, wherein the at least one electrical device includes a temperature sensor.


Patent
WIN Semiconductors Corporation | Date: 2016-04-26

An improved gate metal structure for compound semiconductor devices comprises sequentially a compound semiconductor substrate, a Schottky barrier layer, an insulating layer and a gate metal. The insulating layer has a gate recess. The surrounding and the bottom of the gate recess are defined by the insulating layer and the Schottky barrier layer respectively. The gate metal includes a contact layer formed on the insulating layer, covering the gate recess and contacted with the Schottky barrier layer at the bottom of the gate recess; a first diffusion barrier layer formed on the contact layer; a second diffusion barrier layer formed on the first diffusion barrier layer; and a conduct layer formed on the second diffusion barrier layer. Thereby the reliability of the compound semiconductor devices is enhanced.


Patent
WIN SEMICONDUCTORS Corporation | Date: 2015-09-04

A HBT on a GaAs substrate is presented, wherein its base comprises a first base layer comprising In_(i)Ga_(1-i)As with an Indium content i with a slope s1 and a second base layer on the emitter side comprising In_(i)Ga_(1-j)As with an Indium content j with a slope s2, and an average of s1 is half of the average of s2 or smaller; or the base comprises a first base layer comprising In_(m)Ga_(1-m)As with an Indium content m and a second base layer on the emitter side comprising In_(n)Ga_(1-n)As with an Indium content n, and an average of n is larger than the m at a second base layer side; or the base comprises a first base layer pseudomorphic to GaAs with a bulk lattice constant larger than GaAs, and the emitter comprises a first emitter layer pseudomorphic to GaAs with a bulk lattice constant smaller than GaAs.


Patent
WIN Semiconductors Corporation | Date: 2016-12-06

The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.


Patent
WIN Semiconductors Corporation | Date: 2015-10-15

A high-frequency package comprises a ground lead occupying a side of the high-frequency package; and a signal lead comprising at least a protrusion protruding from a central portion of the signal lead; wherein the ground lead and the signal lead perform as a transmission line, and the at least a protrusion forms capacitance of the transmission line.


Patent
WIN Semiconductors Corporation | Date: 2016-03-15

A protective cover for an acoustic wave device and a fabrication method thereof, for protecting an acoustic wave device having a resonant area during a packaging operation so as to avoid molding compound flowing onto the resonant area of the acoustic wave device. The fabrication method comprises: defining a sacrificial area on the acoustic wave device; forming a sacrificial layer on the sacrificial area; covering a metal covering layer on the sacrificial layer and connecting a bottom rim of the metal covering layer to the acoustic wave device and forming an opening between the bottom rim of the metal covering layer and the acoustic wave device; and removing the sacrificial layer to form a cavity between the metal covering layer and the resonant area by using a chemical solution, wherein the chemical solution enters from the opening between the metal covering layer and the acoustic wave device.


Patent
WIN Semiconductors Corporation | Date: 2016-05-05

A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.


An integrated structure of acoustic wave device and varactor comprises an acoustic wave device and a varactor formed on a first part and a second part of a semiconductor substrate respectively. The acoustic wave device comprises an acoustic wave device upper structure and a first part of a bottom epitaxial structure. The acoustic wave device upper structure is formed on the first part of the bottom epitaxial structure. The varactor comprises a varactor upper structure and a second part of the bottom epitaxial structure. The varactor upper structure is formed on the second part of the bottom epitaxial structure. The integrated structure of the acoustic wave device and the varactor formed on the same semiconductor substrate is capable of reducing the module size, optimizing the impedance matching, and reducing the signal loss between the varactor and the acoustic wave device.


Patent
WIN Semiconductors Corporation | Date: 2016-03-10

A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.


An integrated structure of power amplifier and acoustic wave device comprises: a compound semiconductor epitaxial substrate, a power amplifier upper structure formed on a first side of said compound semiconductor epitaxial substrate, and a film bulk acoustic resonator formed on a second side of said compound semiconductor epitaxial substrate; wherein forming an epitaxial structure on a compound semiconductor substrate to form said compound semiconductor epitaxial substrate; wherein said first side of said compound semiconductor epitaxial substrate and said power amplifier upper structure form a power amplifier; said second side of said compound semiconductor epitaxial substrate and said film bulk acoustic resonator form an acoustic wave device; the integrated structure of power amplifier and acoustic wave device on the same compound semiconductor epitaxial substrate is capable of reducing the component size, optimizing the impedance matching, and reducing the signal loss between power amplifier and acoustic wave device.

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