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Patent
Western Digital Technologies | Date: 2017-01-23

A device includes a non-volatile solid-state memory array comprising a plurality of blocks, each of the plurality of blocks configured to store data in a single-bit per cell mode or a multiple-bit per cell mode, and a controller. The controller is configured to receive write data from a host device, program the write data to a first block of the plurality of blocks of the memory array using the single-bit per cell mode, and perform a data consolidation operation on the first block at least in part by programming at least a portion of the write data together with data stored in a separate second block of the memory array to a third block of the memory array using the multiple-bit per cell mode.


A data storage device including a solid state memory comprising logical block addresses (LBAs) corresponding to boot data accessed by a host during a boot process, and a controller. The controller can be configured to determine the LBAs corresponding to the boot data, and determine whether the solid state memory has reached an end-of-life condition. Upon determining that solid state memory has reached an end-of-life condition, the controller can restrict the host to write to the LBAs corresponding to the boot data during a boot process, and set the solid state memory into a read only mode when the boot process is complete.


Patent
Western Digital Technologies | Date: 2017-01-26

A device includes a non-volatile memory storing a host operating system, a web browser application, a device operating system, and a device application, and control circuitry operable to receive a first request from a host to load the host operating system, provide the device operating system to the host in response to the first request, and receive a second request from the host to load the device application. The device application is configured to transmit a web browser file for the web browser application over the Internet, and generate a host reboot command after transmitting the web browser file.


Patent
Western Digital Technologies | Date: 2015-11-13

The embodiments disclosed herein include an interconnection network that is configured to provide data communication between storage processing units. The disclosed interconnection network can be particularly effective when the storage processing units are configured to locally perform scientific computations. The disclosed interconnection network can enable localized, high throughput, and low latency data communication between storage processing units without overloading the host system.


The disclosure relates to quality of service (QOS) features for a router. The router may determine whether a congestion level of a first interface of the set of network interfaces exceeds a threshold level. Responsive to the congestion level exceeding the threshold level, the router activates a traffic analyzer configured to identify a first session that is present in the data traffic and inserts a set of packets that are part of the first session into a first queue of the set of queues via an expedited communications path over a bus. The router also forwards the set of packets in accordance with the desired quality of service.


Patent
Western Digital Technologies | Date: 2017-04-26

Systems and methods are disclosed for managing and/or accessing distributed data storage. A server computing device or network attached storage (NAS) device may include a message processing module to send and receive electronic-mail (email) messages. The message processing module is configured to cause the NAS device to perform NAS operations based on messages (e.g., email messages from users) and to send email messages with the results of the NAS operations to users.


Patent
Western Digital Technologies | Date: 2017-02-08

A heat sink including a top surface, a first bottom surface configured to thermally contact a first controller having a first height from a circuit board, and a second bottom surface configured to thermally contact a second controller having a second height from the circuit board, wherein the second height is different than the first height.


Patent
Western Digital Technologies | Date: 2016-11-18

In general, techniques are described by which to provide an interface architecture for storage devices. A storage device comprising non-volatile memory, and a hardware controller may be configured to perform various aspects of the techniques. The hardware controller may be configured to read from or write to one or more data registers in a host device to provide a direct communication channel between each of one or more threads executed by one or more processors of the host device and the hardware controller. The hardware controller may further be configured to send a plurality of commands received from the direct communication channel into a hardware queue, and issue access requests based on the plurality of commands to read data from or write data to the non-volatile memory.


Patent
Western Digital Technologies | Date: 2016-02-26

In general, techniques of this disclosure describe usage monitoring of data partitions within a data storage device, such as a data storage device that implements elastic capacity. Techniques may be performed by a host device and a controller of a storage device, where the host device causes the controller to perform the techniques described herein. In general, the controller may create a data partition in the data storage device based on a maximum exposed logical size for the data partition, a maximum allocated logical capacity for the data partition, and an allocated physical capacity for the data partition. The controller may write one or more blocks of data to the data partition. The controller may also send an indication representative of physical space used in the data partition to a host device based on the written one or more blocks of data.


A head gimbal assembly has a laminate flexure that includes a metallic conductive layer that includes a plurality of electrically conductive traces that are elongated and narrow and electrically connected to the read head, and a metallic structural layer that is stiffer than the conductive layer. A first dielectric layer is disposed between the structural layer and the conductive layer. A second dielectric layer substantially covers the conductive layer in a flexure tail bonding region that overlaps a flexible printed circuit (FPC). The structural layer includes a plurality of flexure bond pads that are aligned with, facing, and bonded to corresponding FPC bond pads. The flexure bond pads in the structural layer are electrically connected to the electrically conductive traces in the conductive layer by vias through the first dielectric layer. In certain embodiments, the flexure tail is folded upon itself in the flexure tail bonding region.

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