Irvine, CA, United States

Western Digital Technologies

wdc.com
Irvine, CA, United States

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Patent
Western Digital Technologies | Date: 2017-01-23

A device includes a non-volatile solid-state memory array comprising a plurality of blocks, each of the plurality of blocks configured to store data in a single-bit per cell mode or a multiple-bit per cell mode, and a controller. The controller is configured to receive write data from a host device, program the write data to a first block of the plurality of blocks of the memory array using the single-bit per cell mode, and perform a data consolidation operation on the first block at least in part by programming at least a portion of the write data together with data stored in a separate second block of the memory array to a third block of the memory array using the multiple-bit per cell mode.


A data storage device including a solid state memory comprising logical block addresses (LBAs) corresponding to boot data accessed by a host during a boot process, and a controller. The controller can be configured to determine the LBAs corresponding to the boot data, and determine whether the solid state memory has reached an end-of-life condition. Upon determining that solid state memory has reached an end-of-life condition, the controller can restrict the host to write to the LBAs corresponding to the boot data during a boot process, and set the solid state memory into a read only mode when the boot process is complete.


Patent
Western Digital Technologies | Date: 2017-01-26

A device includes a non-volatile memory storing a host operating system, a web browser application, a device operating system, and a device application, and control circuitry operable to receive a first request from a host to load the host operating system, provide the device operating system to the host in response to the first request, and receive a second request from the host to load the device application. The device application is configured to transmit a web browser file for the web browser application over the Internet, and generate a host reboot command after transmitting the web browser file.


The disclosure relates to quality of service (QOS) features for a router. The router may determine whether a congestion level of a first interface of the set of network interfaces exceeds a threshold level. Responsive to the congestion level exceeding the threshold level, the router activates a traffic analyzer configured to identify a first session that is present in the data traffic and inserts a set of packets that are part of the first session into a first queue of the set of queues via an expedited communications path over a bus. The router also forwards the set of packets in accordance with the desired quality of service.


Patent
Western Digital Technologies | Date: 2017-04-26

Systems and methods are disclosed for managing and/or accessing distributed data storage. A server computing device or network attached storage (NAS) device may include a message processing module to send and receive electronic-mail (email) messages. The message processing module is configured to cause the NAS device to perform NAS operations based on messages (e.g., email messages from users) and to send email messages with the results of the NAS operations to users.


Patent
Western Digital Technologies | Date: 2017-02-08

A heat sink including a top surface, a first bottom surface configured to thermally contact a first controller having a first height from a circuit board, and a second bottom surface configured to thermally contact a second controller having a second height from the circuit board, wherein the second height is different than the first height.


Patent
Western Digital Technologies | Date: 2017-03-03

Systems and methods for determining a physical block address (PBA) of a non-volatile memory (NVM) to enable a data access of a corresponding logical block address (LBA) are described. One such method includes generating a first physical block address (PBA) candidate from a LBA using a first function; generating a second physical block address (PBA) candidate from the LBA using a second function; and selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.


A head gimbal assembly has a laminate flexure that includes a metallic conductive layer that includes a plurality of electrically conductive traces that are elongated and narrow and electrically connected to the read head, and a metallic structural layer that is stiffer than the conductive layer. A first dielectric layer is disposed between the structural layer and the conductive layer. A second dielectric layer substantially covers the conductive layer in a flexure tail bonding region that overlaps a flexible printed circuit (FPC). The structural layer includes a plurality of flexure bond pads that are aligned with, facing, and bonded to corresponding FPC bond pads. The flexure bond pads in the structural layer are electrically connected to the electrically conductive traces in the conductive layer by vias through the first dielectric layer. In certain embodiments, the flexure tail is folded upon itself in the flexure tail bonding region.


Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.


Patent
Western Digital Technologies | Date: 2017-04-05

A method may include forming, by a processor, a logical data address container comprising a plurality of logical data addresses. Each logical data address corresponds to a respective physical data address. The method also may include specifying, by the processor, a fully specified physical data address corresponding to a first logical data address of the plurality of logical data addresses. The method further may include specifying, by the processor, partially specified physical data addresses corresponding to the other logical data addresses of the plurality of logical data addresses. The partially specified physical data addresses may include sufficient address information to specify physical data addresses not directly adjacent to the fully specified physical data address. The method also may include storing the fully specified physical data address and the plurality of partially specified physical data addresses in a logical to physical data address translation table.

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