Camarillo, CA, United States

Vitesse Semiconductor

vitesse.com
Camarillo, CA, United States

Vitesse Semiconductor is a fabless American semiconductor company based in Camarillo, California, which develops high-performance Ethernet integrated circuits solutions for Carrier, Enterprise and Internet of Things networks. Wikipedia.

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Patent
Vitesse Semiconductor | Date: 2014-09-30

A transparent clock may be provided between edge nodes of a non-precision time protocol network, with an arrival time of a packet at an edge of the non-precision time protocol network carried in a reserved field of a packet.


Patent
Vitesse Semiconductor | Date: 2014-09-30

A transparent clock converter is interposed between a non-precision time protocol (non-PTP) enabled network node and other portions of the network. The transparent clock converter effectively converts the non-PTP node into a transparent clock node. In some embodiments the transparent clock converter includes physical layer devices, but not media access controllers.


Patent
Vitesse Semiconductor | Date: 2014-01-21

Precision Timing Protocol (PTP) related functions for use in packet communications carried in part by a microwave communications link include setting of time of day values across the microwave link and providing transparent clock functions. The PTP functions may be used for synchronizing radio base stations in a cellular network. The transparent clock can bridge Ethernet switches associated with microwave stations providing the microwave communications link.


Patent
Vitesse Semiconductor | Date: 2012-04-04

A physical layer communication device (PHY) transmits and receives signal to and from a communication link using a synchronous protocol. The PHY communicates with a higher-layer device using a packet protocol. Timestamp values contained in timing-related messages in some packets are written or modified by the PHY. Delays incurred in transmitting and receiving the packets are predicted and used in setting the timestamp values.


Patent
Vitesse Semiconductor | Date: 2012-09-14

Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.


Patent
Vitesse Semiconductor | Date: 2013-12-19

Methods and devices generate cyclic redundancy check (CRC) values for a sequence of parallel words of data. The data words may have only some of the bits enabled. The input words are preconditioned, and then a common block generates a CRC remainder value. A specific preconditioning is selected based on the number of enabled bits. Additional post-processing may be performed to the CRC remainder.


Patent
Vitesse Semiconductor | Date: 2014-02-03

A slave communication device may transmit a packet to the master communication device, with the packet including a transmission time field and a correction field. The transmission time field may contain a value indicative of an approximate time of transmission of the packet by the slave communication device, and the correction field may contain a value indicative of a difference between the approximate time of transmission and an actual time of transmission of the packet by the slave communication device.


Patent
Vitesse Semiconductor | Date: 2014-10-28

Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.


Patent
Vitesse Semiconductor | Date: 2012-05-14

A system and method for squelching a recovered clock in an Ethernet network. In one embodiment the invention provides a method for squelching a recovered clock in an Ethernet network comprising a local node coupled to a remote node by a link, the method including receiving a descrambler status signal, receiving a remote receiver status signal, receiving a link status signal, and squelching the recovered clock signal based on the descrambler status signal, the remote receiver status signal, and the link status signal.


Patent
Vitesse Semiconductor | Date: 2014-09-23

Device and methods determine timing parameters and associated timing actions from timing messages in communication packets. The timing messages may be encapsulated with plurality of communication protocols. An example timing message may be an IEEE 1588 timing message encapsulated in an Internet protocol packet encapsulated in an Ethernet protocol packet. The protocols are matched in classifier blocks by comparing portions of the packet to bit values or ranges of values. Operation of other than the first classifier block depends on results of matching in the preceding block by using offset values passed between blocks that indicate starting points for the matching. The final classifier block matches values in timing messages to identify timing parameters and associated timing actions in the message.

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