Vignans University Vfstr University

Guntūr, India

Vignans University Vfstr University

Guntūr, India
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Nanireddy G.,QIS Institute of Technology | Vaddempudi K.R.,QIS Institute of Technology | Rukmini M.S.S.,Vignans University Vfstr University
Journal of Advanced Research in Dynamical and Control Systems | Year: 2017

The reliability of any Communication system or digital signal processing system mostly depends on the design of filters that are fault tolerant. FIR filters with error correction codes that operate in parallel have been developed that increase the redundancy and size of the system. These filters used error correction codes that have forward error correction capability and as such fault tolerance that increased the chip size. The proposed method uses less number of redundant modules than the existing ones and reduces the area of such filters by approximately 21.18% that reduces the cost of the system implementation almost by the same amount. © 2017, Institute of Advanced Scientific Research, Inc. All rights reserved.


Bajidbi S.,Vignans University Vfstr University | Rukmini M.S.S.,Vignans University Vfstr University | Ratna Babu Y.,Vignans University Vfstr University
Lecture Notes in Electrical Engineering | Year: 2016

Reversible logic is gaining more importance day by day, because of its feature of low power dissipation which is the basic need in designing nano electronic devices, bioinformatics, low power CMOS designs and quantum computing. Reversible logic is one which realizes n-input n-output functions that map each possible input vector to a unique output vector. It is a promising computer design paradigm for constructing arithmetic and logic units which are the basic building blocks of computer that do not dissipate heat. After designing a system, it is also equal important to test it. In this paper reversible ALU (Arithmetic and Logical Unit) performing four operations (Addition, Multiplication, Subtraction and Bit wise- AND) is implemented and the simulated results like power consumed, delay and area obtained are compared with that of conventional ALU. Testing is also done on proposed reversible ALU by using BILBO (Built—in Logic Block Observer) blocks, which was the first BIST (Built-in Self Test) architecture to be proposed and undergo wide spread use. The proposed reversible ALU is implemented and simulated using Verilog HDL in Xilinx 13.4 version. © Springer India 2016.

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