Vemana Institute of Technology

Bangalore, India

Vemana Institute of Technology

Bangalore, India
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Thakur G.,Vemana Institute of Technology | Sarvagya M.,Bangalore University
2016 IEEE Annual India Conference, INDICON 2016 | Year: 2016

The tremendous growth of broadcast and multicast traffic applications (audio, video, IPTV, teleconferencing etc) over the internet has created an imperative demand for high performance switches. Various switching architectures have been proposed for multicast traffic support. A Digital Cross Connect (DCS) is a crossbar-based switching device and has been considered the most suitable architecture because of its low cost and internal multicast capabilities. In this paper we have proposed the design of a Digital Cross Connect (DCS) switch for broadcast and multicast traffic support. The proposed DCS design has been simulated for different traffic modes (multicast and broadcast) using Verilog Hardware Description Langauage (HDL) in Xilinx software. Further, the design can be implemented on the FPGA board in order to achieve flexibility, adaptibility and scalability. © 2016 IEEE.

Lakshmi Shree K.,Vemana Institute of Technology | Penubaku L.,Bangalore University | Nandihal G.,Bangalore University
2016 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2016 | Year: 2017

The current automobile industry aims at using wireless communication to enable intelligence for creating next generation automobiles. The industries are intending to build intelligent transport system a real-Time communication system to transmit and receive instant information from a current vehicle and its surrounding. In this direction, the proposed work is to implement Zigbee, an IEEE 802.15.4 standard in automobiles for data communication among the vehicles. The choice of Zigbee is due to its gaining popularity for its features like, low-cost, low-power, controlling and remote monitoring features which works will for inter-vehicular communication applications mainly in short range communication category. The paper presents a design and implementation of Zigbee area network(ZAN) and also pays attention in providing a secure system. © 2016 IEEE.

Metan J.,Visvesvaraya Technological University | Narasimha Murthy K.N.,Vemana Institute of Technology
2015 International Conference on Emerging Research in Electronics, Computer Science and Technology, ICERECT 2015 | Year: 2015

The area of wireless sensor network is already shrouded with various issues e.g. energy issues, routing issues, QoS issues, and security issues. Although in past there were evolution of various secure techniques, but majority of the technique were sophisticated cryptographic implementations where time and space complexities were less emphasized. This paper presents a simple and a novel technique called as MLKS i.e. Multi Level Key Security that applies simple set theory and key distribution mechanism for securing the data aggregation in wireless sensor network. The technique is also applicable on multiple security standards supporting 128, 216, 160, or 512 bits of key size. The outcome of the proposed system is compared with the most significant work to find the proposed system outperforms the existing system with respect to computational time and storage cost. © 2015 IEEE.

Parameshwara M.C.,Vemana Institute of Technology | Srinivasaiah H.C.,Dayananda Sagar College of Engineering
Proceedings of the 3rd International Conference on Devices, Circuits and Systems, ICDCS 2016 | Year: 2016

In this paper we propose a novel approach to compress the size of sine Read Only Memory (sROM) using a Sine Linear-Phase-Offset Difference (SLPOD) method. The sROM is a sine look-up table memory and is used to store sine approximation errors corresponding to an angle [0, π/2). The sine approximation errors can be computed by using the state-of-the-art sROM compression techniques. The Sine Linear-Phase Difference (SLPD) method is one such compression technique that saves two bits in the sROM output word. The SLPOD method is a novel compression technique derived based on the traditional SLPD technique. In a proposed method the sROM stores the values of sine approximation error that are derived using the SLPOD approach. This approach of deriving sine approximation error greatly minimizes the maximum value of difference that occurs between the quadrant sine function and the linear-phase. To obtain sine approximation error using SLPOD approach we divide the linear-phase 'x' (where x ϵ [0, 1)) into 'k' segments (where k is chosen as positive integer powers-of-2) and each segment is offset by a constant value (ϵ [0, 1)). Using this proposed SLPOD approach we can save N = log2(k) bits in sROM output word. © 2016 IEEE.

Parameshwara M.C.,Vemana Institute of Technology | Srinivasaiah H.C.,Dayananda Sagar College of Engineering
Journal of Circuits, Systems and Computers | Year: 2016

A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118(Formula presented.)(Formula presented.)W, with a delay of 606 ps, with an area of 33.1(Formula presented.)(Formula presented.)m2, resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage (Formula presented.)(Formula presented.)V, input signal frequency (Formula presented.)(Formula presented.)MHz is used. This 1-bit FA is designed and implemented using Cadences’ 90(Formula presented.)nm “generic-process-design-kit” (GPDK). © 2017 World Scientific Publishing Company

Sowmya Naik P.T.,City Engineering College | Narasimha Murthy K.N.,Vemana Institute of Technology
Advances in Intelligent Systems and Computing | Year: 2016

A base station is the core heart of the operation in cellular communication system. Various components e.g. base transceiver station, base station controller, mobile station controller are basically a sophisticated hardware device which require a massive amount of energy just to initiate, manage, and terminate an IP communication over mobile network. Inspite of presence of massive archives of literatures towards addressing energy consumption, there are very few evidence of standard prototype that can be actually adopted in real sense. Therefore, we present an analytical model for jointly addressing traffic normalization problem and energy efficiency problem using simple stochastic geometry. Supported by discussion of algorithms, the presented technique was also compared with one of the most recent study to find its superior performance with respect to energy consumption and processing time. © Springer International Publishing Switzerland 2016.

Sunil H.,Vemana Institute of Technology | Hiremath S.G.,East West Institute of Technology
Proceedings of the 2015 International Conference on Applied and Theoretical Computing and Communication Technology, iCATccT 2015 | Year: 2015

Medical images contain more data and therefore, to save the transmission time, storage capacity and saving the time, an efficient image compression method is required. In this work we introduce a new algorithm for image compression decompression (reconstruction) based on JPEG 2000 standards. The proposed algorithm is named as Decompression based composite splitting Algorithm (DBCA) which is the combination of the RLTA (Repetitive Loss-Thresholding algorithm) and DDA (Denoising Dividing Algorithm). In the first step of the proposed algorithm, the image is divided into sub-parts. These sub-parts of the image are treated as smaller size minimization problem. Each sub part of the image reconstructed individually and finally all the reconstructed parts of the image are combined together to get the reconstructed image. The visual and mathematical results are shown which are superior to the existing method for image compression and reconstruction. © 2015 IEEE.

Ramesha K.,Vemana Institute of Technology | Raja K.B.,University Visvesvaraya College of Engineering
Communications in Computer and Information Science | Year: 2011

The face recognition system is used to create a national database for the purpose of identity cards, voting in an electoral systems, bank transaction, food distribution system, control over secured areas etc. In this paper we propose the Face Recognition System using Discrete Wavelet Transform and Fast PCA (FRDF). The Discrete Wavelet Transform is applied on face images of Libor Spacek database and only LL subband is considered. Fast Principal Component Analysis using Gram-Schmidt orthogonalization process is applied to generate coefficient vectors. The Euclidean Distance between test and database face image coefficient vectors are computed for face recognition based on the threshold value. It is observed that the face recognition rate is 100% and the proposed algorithm for the computation of eigenvalues and eigenvectors improves the computational efficiency as compared to Principal Component Analysis (PCA) with same Mean Square Error (MSE). © 2011 Springer-Verlag.

Vijayasimha Reddy B.G.,Vemana Institute of Technology | Sharma K.V.,University Visvesvaraya College of Engineering | Yella Reddy T.,Vemana Institute of Technology
Materials and Design | Year: 2014

The response and energy absorption capacity of cellular sandwich panels that comprises of silk-cotton wood skins and aluminum honeycomb core are studied under quasi-static and low velocity impact loading. Two types of sandwich panels were constructed. The Type-I sandwich panel contains the silk-cotton wood plates (face plates) with their grains oriented to the direction of loading axis and in the case of Type-II sandwich panel, the wood grains were oriented transverse to the loading axis. In both of the above cases, aluminum honeycomb core had its cell axis parallel to the loading direction. The macro-deformation behavior of these panels is studied under quasi-static loading and their energy absorption capacity quantified. A series of low velocity impact tests were conducted and the dynamic data are discussed. The results are then compared with those of quasi-static experiments. It is observed that the energy absorption capacity of cellular sandwich panels increases under dynamic loading when compared with the quasi-static loading conditions. The Type-I sandwich panels tested in this study are found to be the better impact energy absorbers for low velocity impact applications. © 2014 Elsevier Ltd.

Ambareesh S.,Vemana Institute of Technology | Fathima J.,Vemana Institute of Technology
Procedia Computer Science | Year: 2016

The performance of computing devices is increasing day by day, the storage devices are not capable to reach with this benchmark. The compute and storage resources are forming two parts of the shared network. This paper is presenting a storage middleware called HyCache+ to reduce the high bi-section bandwidth of the parallel computing systems. The middleware uses Programmable Operating System (POSIX) interface to the end users to swap the data with the high capacity network attached storage. The system uses a 2-layer scheduling approach. The HyCache+ can be deployed on the IBM Blue Gene / P supercomputers for the performance comparison. © 2016 Published by Elsevier B.V.

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