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Sathyamurthy R.,Hindustan University | Nagarajan P.K.,Saengineering College | Subramani J.,Saengineering College | Vijayakumar D.,Veltech Multitech Drrangarajan Drsakunthala Engineering College | Mohammed Ashraf Ali K.,Hindustan University
Energy Procedia | Year: 2014

In this paper the effect of water mass on the performance of triangular pyramid solar still with and without latent heat energy storage was experimentally investigated. For comparing the productivity of solar still with and without LHTESS a solar still is designed, fabricated. Experiments are conducted in hot and humid climate of Chennai, India. It is found that there is an increase of production of fresh water with decrease in water mass. There is an increase of about 35% in production of fresh water with LHTESS than that of solar still without LHTESS. Also it was found that during the off shine period the fresh water produced from the still is higher compared to higher water mass. The solar still with and without LHTESS were found to be 5.5 L/m2day and 3.5 L/m2day. © 2014 Published by Elsevier Ltd.


Gowri D.,Veltech Multitech Drrangarajan Drsakunthala Engineering College | Mohammed Abbas A.,Veltech Multitech Drrangarajan Drsakunthala Engineering College
2013 International Conference on Information Communication and Embedded Systems, ICICES 2013 | Year: 2013

While the issue of Trojan ICs has been receiving increasing amounts of attention, the overwhelming majority of anti-Trojan measures aim to address the problem during verification. While such methods are an important part of an overall anti-Trojan strategy, it is statistically inevitable that some Trojans will escape verification-stage detection, in particular in light of the increasing size and complexity of system-on-chip (SOC) solutions and the increasing use of third-party designs. In contrast with much of the previous work in this area, we specifically focus on run-time methods to identify the attacks of a Trojan and to adapt the system and respond accordingly. We describe a solution including a bus architecture in which the arbitration, address decoding, multiplexing, wrapping, and other components protect against malicious use of the bus. © 2013 IEEE.


Raj S.N.,Veltech Multitech Drrangarajan Drsakunthala Engineering College | Ashok S.,Veltech Multitech Drrangarajan Drsakunthala Engineering College | Vengateswarlu P.B.,Veltech Multitech Drrangarajan Drsakunthala Engineering College | Rao G.V.,Veltech Multitech Drrangarajan Drsakunthala Engineering College
Journal of Chemical and Pharmaceutical Sciences | Year: 2016

Low level data processing purposes are like FIR filtering, recognition of patterns or correlation, whereas the parallel implementation is upheld by the design matched distinct intention arithmetic; elevated throughput FPGA routes facilely output waveform even for the most advanced DSP processors. In this paper examine a high-speed non-linear Adaptive median filter implementation is presented. Next the Adaptive Median Filter solves the dual intention of removing the impulse noise from the image and cutting to distortion in the image. Adaptive Median Filtering can be accomplish the filtering procedure of an image corrupted alongside impulse noise.


Raj C.S.,Veltech Multitech Drrangarajan Drsakunthala Engineering College | Kirubakaran S.J.,Veltech Multitech Drrangarajan Drsakunthala Engineering College | Vengateswarlu P.B.,Veltech Multitech Drrangarajan Drsakunthala Engineering College
Journal of Chemical and Pharmaceutical Sciences | Year: 2016

We propose new technique for clock gating. Clock gating is helpful for reducing power consumed in digital system. There are three technique used (i) Synthesis Based method (ii) Data driver Method (iii) Auto gated flip flop (AGFF). The Auto gated Flip flop can be distributed in the clock distribution Network. Clock distribution use current other than voltage by giving global clock. With auto gated flip flop. It is used for power sowing. Clock gating can be tested in current mode pulsed flip flop with enable (CMPFFE) using 48nm CMOS technology. Look Ahead clock gating (LACG) computers the clock signal at one cycle ahead of time. Flip flop depends on the present cycle. This model can be characters by power saved in FF. This technique is based a data to clock togging. Majority of FF fall in positive Region Experimentation in industry- scale data display 22.5% reduction of clock power.


Senthilkumar B.,St Peters University | Rajamani V.,Veltech Multitech Drrangarajan Drsakunthala Engineering College
Journal of Theoretical and Applied Information Technology | Year: 2014

This paper describes about novel VLSI implementation of key based substitution box(S-box) for Substitution-Permutation supported private key cryptosystems. Our design uses the mathematical properties of the (8, 4) Extended Hamming Code and its error control logic to produce 256 unique elements in one Sbox over finite Galois Field (GF) (28). Row - Column Index based selection of four 8bit vectors and their modulo-2 addition is employed for both byte substitution and its inverse. Proposed substitution method provides optimal substitution output probability with 40320 S-boxes for a single message byte over GF (28). Proposed method removes the direct relationship between linear and algebraic expressions of S-box vectors and byte substitution technique of S-box for strengthening our structure against linear and differential attacks. High nonlinearity penetration of original input message bits is achieved by applying shift based key schedules for round transformations and bit permutation based S-box vectors in proposed byte substitution. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA (XC3S500E-PQG208) and the simulation results are shown. Various substitution output results are shown by proposed S-boxes simulation for its optimal application. This paper concludes that novel Key dependent Substitution Box using Error Control Algorithm is an alternative solution to the existing threats on cryptography algorithms. © 2005 - 2014 JATIT & LLS. All rights reserved.


Rajendran S.,Dr. M.G.R. Educational and Research Institute | Balasubramanian K.,Veltech Engineering College | Rajeswari N.,Veltech Multitech Drrangarajan Drsakunthala Engineering College
International Journal of Applied Engineering Research | Year: 2015

A metaheuristics approach is chosen in cases where the exact methods are not enough to provide a solution. It is an iterative process to efficiently produce solutions which are closer to the global optimum.. This paper addresses the application of generic algorithm for a parallel machine flow line scheduling problem using the algorithm proposed for minimizing the makespan. Sequencing of operations to attain a feasible minimum makespan is one of the important requirements to achieve effective production from process planning. Since the problem is NP-hard, it is chosen to adopt genetic algorithm as it is one of the proven methods to search for a feasible optimal solution to the objective function. This paper addresses the methodology to obtain a near optimal sequence of jobs for an allocation of constrained resources with the objective of minimization of overall completion time or makespan. The methodology is based on creating a group of random solutions and uses the genetic operators of cross over and mutation to improve the solutions till an acceptable fitness level is reached. As the implementation of the local search is time consuming, a tool based on visual basic was developed to do the search faster. The tool had the options to search exhaustively or using the genetic algorithm methods. The computational experiments deployed indicate that it is feasible with the proposed methodology and procedures to arrive at better solutions faster than the conventional methods. © Research India Publication.


Ramachandran R.,Veltech Multitech Drrangarajan Drsakunthala Engineering College | Ruban T.D.,Veltech Multitech Drrangarajan Drsakunthala Engineering College
2013 International Conference on Information Communication and Embedded Systems, ICICES 2013 | Year: 2013

Ad Hoc Networks are a new generation of networks offering unrestricted mobility without any underlying infrastructure. Due to lack of centralized control, secured communication in mobile ad hoc network is a crucial issue due to dynamic nature of the network topology. While the routing aspects of mobile ad hoc networks (MANETs) are already well understood, the research activities about security in MANETs are still at their beginning. MANETs pose a number of new security problems in addition to the problems of regular networks. In this paper, we propose an effective security AODV algorithm called ES-AODV to enhance the data security. Simulation results show that our algorithm provides a reasonably good level of security and performance. © 2013 IEEE.


Kabeer M.,B S Abdurrahman Crescent Engineering College | Rajamani V.,Veltech Multitech Drrangarajan Drsakunthala Engineering College | Bose S.,Anna University
Journal of Optoelectronics and Advanced Materials | Year: 2014

A two-dimensional numerical modeling of a uniformly doped nanoscale Double-Gate SOI n-MOSFET under illuminated condition including quantum mechanical effects has been developed. A self-consistent solution of 2-D Poisson-Schrödinger equation has been obtained. Finite differential method is used in solving the Schrödinger equation using mode space approach due to which size of the problem is reduced and sufficient accuracy is obtained. Leibmann's iteration method is used in solving Poisson equation with proper boundary conditions. The exact potential profile of the device under illuminated condition has been computed numerically. The electric field profile along the length and width of the channel and mobility of the carriers have also been studied extensively under illuminated condition to have an in depth analysis. Calculations are being carried out to examine the effect of illumination on the current-voltage characteristics, conduction band vs sub-band energy profile and sub-band electron density. The accuracy of the model has been verified by comparing the results with that calculated by nanomos 2.5 device simulator. Due to effect of photo generation, the device characteristics are strongly influenced. The proposed model is fairly accurate and can be used for accurate simulation of Opto Electronic Integrated Circuits (OEIC) using uniformly doped DG SOI n-MOSFET Photo detector.


Senthilkumar B.,St Peters University | Rajamani V.,Veltech Multitech Drrangarajan Drsakunthala Engineering College
International Journal of Engineering and Technology | Year: 2014

This paper describes about novel key expansion and its inversion technique for private key cryptosystems. Our design uses (8, 4) Extended Hamming Code and its error control logic to produce memory efficient key schedule generation algorithm. A mathematical relationship between 4bit word and its corresponding 4bit parity bits is shown. Simplicity, symmetry elimination, diffusion and non-linearity of the proposed key expansion technique are described as the key schedule generation criteria. Proposed method removes the usage of S-box to reduce the working memory of the algorithm. High nonlinearity penetration of original input message bits is achieved by applying modulo2 addition of code based key schedules for each round transformations. Security strength among these key schedules is achieved by intentional bit inversions among them with beyond the error correcting limitations of chosen code. Comparative results between proposed design and Rijndael algorithm is illustrated with the aid of Xilinx Simulation tool. This paper concludes that novel key generation technique by Error Control Algorithm of wireless communication channel is an alternative solution to the cryptosystems without S-box substitution and any lookup tables.


Senthilkumar B.,St Peters University | Rajamani V.,Veltech Multitech Drrangarajan Drsakunthala Engineering College
Journal of Theoretical and Applied Information Technology | Year: 2015

This paper presents a hardware implementation for Encoder and Decoder of the cryptography technique using versatile Error Control Algorithms of Block Codes used in wireless communication networks. This work is focused on the designing of VLSI based hardware implementable and more secured alternative of existing software based symmetric cryptography techniques using DES (Data Encryption Standard) and AES (Advanced Encryption Standard Algorithm). In this design process, traditional methods of sub key generation using bit shifting along with modulo 2 addition, performance of padding and puncturing the bits of words are done so as to maintain the reliability of the design at par with conventional technique. In this design, (7,4) Block code with hamming code algorithm is considered as it has very low probability to retrieve originality without specific syndrome analysis and can be easily penetrated between any number of bits of original message as required by the Cryptography. This design is simulated and the synthesis report is generated using Verilog coding of Xilinx ISE software and the modules and results are illustrated. The report and result reveals that the proposed design will occupy very lesser number of components with reliable performance. This will lead to the small amount of power consumption and compactness in hardware implementation. Also, it is observed that the even though the used key size is small, the complexity for the intruder to retrieve the original message is greatly increased by incorporating the variety of hardware diversifying practice without sacrificing the strength of required cryptography technique. The test result shows the significance of the proposed design as the same set of message never produces the same set of cipher text. So that the computational attacks using software based iteration can not be used to track the plain text. © 2005 - 2015 JATIT & LLS. All rights reserved.

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