Krishnamoorthy D.,Vel Technology Drrr And Drsr University |
Prasanna V.,Vel Technology Drrr And Drsr University |
Ramachandran K.,Vel Technology Drrr And Drsr University |
Pal S.,Vel Technology Drrr And Drsr University
IEICE Electronics Express | Year: 2015
In the conventional second order, single bit, discrete ΔΣ Modulator (DSM), the sampling of input signal and DSM operation is performed at the same frequency. In this conventional DSM, signal to noise ratio (SNR) starts falling down rapidly when the modulus of normalized input signal is above 0.47. The integrators output become arbitrarily large which make the system unstable by saturating the operational amplifiers used in the circuit. There are recent papers in which the modulus of normalized input signal can be increased up to 0.7. In the present paper, a second order DSM with different sampling frequency and DSM clock frequency is proposed. The operating period of the proposed DSM is proportional to the sampled analog input signal. The proposed DSM can operate for the full range of normalized input signal (−1 to +1), has better signal to noise ratio (SNR) in the higher range and can be realized using cmos circuit of supply voltage ±1.5 V. The maximum bound on the integrators outputs is 1.5 V. The proposed DSM has unidirectional output and the oscillation at the output for zero input is no longer present and these properties are essential to drive stepper motors which are the actuators for control valves in industry. In the output spectrum near the signal frequency, the noise level is well below the signal level. The proposed DSM results in low power, stable full range operation with better SNR and power spectral density (PSD). © IEICE 2015.