Veeco Instruments | Date: 2015-11-30
Methods for stress control in thin silicon (Si) wafer-based semiconductor materials. By a specific interrelation of process parameters (e.g., temperature, reactant supply, time), a highly uniform nucleation layer is formed on the Si substrate that mitigates and/or better controls the stress (tensile and compressive) in subsequent layers formed on the thin Si substrate.
Plansee Group and Veeco Instruments | Date: 2017-02-15
The invention is related to a heating element (10) comprising a heating body (20) which is directly covered at least partly with a porous sintered coating (30), wherein the heating body (20) the porous sintered coating (30) each comprises at least 90 % by weight of tungsten.
Veeco Instruments | Date: 2016-08-16
Improvements to the heating uniformity of a wafer carrier for a chemical vapor deposition (CVD) system can be made based on a computational thermal model built according physical and operational characteristics of the CVD system. Operation of the thermal model is simulated, where a process recipe to be carried out on the CVD system is modeled, including heat transfers taking place in the virtual CVD system, to produce a set of thermal-spatial non-uniformities in at least one region of interest of a virtual wafer carrier. Structural corrections to be made to the pocket floor of each of the at least one wafer retention pocket are determined based on the set of thermal-spatial non-uniformities and on a predefined thermal-pocket floor relation that defines at least one design rule for correcting the pocket floor to achieve an increase in thermal uniformity throughout the at least one region of interest.
Veeco Instruments | Date: 2015-07-30
Embodiments include systems and methods for producing semiconductor wafers having reduced quantities of point defects. These systems and methods include a tunable ultraviolet (UV) light source, which is controlled to produce a raster of a UV light beam across a surface of a semiconductor wafer during epitaxial growth to dissociate point defects in the semiconductor wafer. In various embodiments, the tunable UV light source is configured external to a Metal Organic Chemical Vapor Deposition (MOCVD) chamber and controlled such that the UV light beam is directed though a window defined in a wall of the MOCVD chamber.
Veeco Instruments | Date: 2016-09-15
A wafer carrier for a plurality of wafers, the wafer carrier having a platen with a plurality of openings and a plurality of wafer retention platforms, the platen configured to rotate about a first axis, the plurality of wafer retention platforms configured to rotate about respective second axes, each of the wafer retention platforms rotatably coupled to one of the plurality of openings by friction reducing bearings, the platen and the plurality of wafer retention platforms and the friction reducing bearings all being constructed of the same material.
Veeco Instruments | Date: 2016-08-24
A chemical vapor deposition system is disclosed herein. The chemical vapor deposition system has a plurality of reaction chambers to operate independently in the growth of epitaxial layers on wafers within each of the reaction chambers for the purpose of reducing processing time while maintaining the quality necessary for the fabrication of high-performance semiconductor devices.
Veeco Instruments | Date: 2017-01-11
A wafer carrier assembly for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition (CVD), the wafer carrier assembly includes a wafer carrier body formed symmetrically about a central axis, and including a generally planar top surface that is situated perpendicularly to the central axis and a planar bottom surface that is parallel to the top surface. At least one wafer retention pocket is recessed in the wafer carrier body from the top surface. Each of the at least one wafer retention pocket includes a floor surface and a peripheral wall surface that surrounds the floor surface and defines a periphery of that wafer retention pocket. At least one thermal control feature includes an interior cavity or void formed in the wafer carrier body and is defined by interior surfaces of the wafer carrier body.
Veeco Instruments | Date: 2015-10-30
This disclosure provides various methods for improved etching of spin-transfer torque random access memory (STT-RAM) structures. In one example, the method includes (1) ion beam etch of the stack just past the MTJ at near normal incidence, (2) a short clean-up etch at a larger angle in a windowed mode to remove any redeposited material along the sidewall that extends from just below the MTJ to just above the MTJ, (3) deposition of an encapsulant with controlled step coverage to revert to a vertical or slightly re-entrant profile from the tapered profile generated by the etch steps, (4) ion beam etch of the remainder of the stack at near normal incidence while preserving the encapsulation along the sidewall of the MTJ, (5) clean-up etch at a larger angle and windowed mode to remove redeposited materials from the sidewalls, and (6) encapsulation of the etched stack.
Veeco Instruments | Date: 2016-12-16
A rotating disk reactor for chemical vapor deposition includes a vacuum chamber and a ferrofluid feedthrough comprising an upper and a lower ferrofluid seal that passes a motor shaft into the vacuum chamber. A motor is coupled to the motor shaft and is positioned in an atmospheric region between the upper and the lower ferrofluid seal. A turntable is positioned in the vacuum chamber and is coupled to the motor shall so that the motor rotates the turntable at a desired rotation rate. A dielectric support is coupled to the turntable so that the turntable rotates the dielectric support when driven by the shaft. A substrate carrier is positioned on the dielectric support in the vacuum chamber for chemical vapor deposition processing. A heater is positioned proximate to the substrate carrier that controls the temperature of the substrate carrier to a desired temperature for chemical vapor deposition.
Veeco Instruments | Date: 2016-10-10
A PVD chamber for growing a magnetic film of NiFe alloy at a growth rate of greater than 200 nm/minute produces a film exhibiting magnetic skew of less than plus or minus 2 degrees, magnetic dispersion of less than plus or minus 2 degrees, DR/R of greater than 2 percent and film stress of less than 50 MPa. NiFe alloy is sputtered at a distance of 2 to 4 inches, DC power of 50 Watts to 9 kiloWats and pressure of 3 to 8 milliTorr. The chamber uses a unique field shaping magnetron having magnets arranged in outer and inner rings extending about a periphery of the magnetron except in two radially opposed regions in which the inner and outer rings diverge substantially toward a central axis of the magnetron.