Zaltbommel, Netherlands
Zaltbommel, Netherlands

Vector Fabrics, B.V. is a software-development tools vendor based in Eindhoven, The Netherlands. They develop tools for programming multicore platforms. Vector Fabrics says to help software developers and OEMS that struggle to write error-free and efficient code for multicore and manycore processors. Wikipedia.


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Grant
Agency: European Commission | Branch: FP7 | Program: JTI-CP-ARTEMIS | Phase: SP1-JTI-ARTEMIS-2013-AIPP5 | Award Amount: 93.92M | Year: 2014

Embedded systems are the key innovation driver to improve almost all mechatronic products with cheaper and even new functionalities. Furthermore, they strongly support todays information society as inter-system communication enabler. Consequently boundaries of application domains are alleviated and ad-hoc connections and interoperability play an increasing role. At the same time, multi-core and many-core computing platforms are becoming available on the market and provide a breakthrough for system (and application) integration. A major industrial challenge arises facing (cost) efficient integration of different applications with different levels of safety and security on a single computing platform in an open context. The objective of the EMC project (Embedded multi-core systems for mixed criticality applications in dynamic and changeable real-time environments) is to foster these changes through an innovative and sustainable service-oriented architecture approach for mixed criticality applications in dynamic and changeable real-time environments. The EMC2 project focuses on the industrialization of European research outcomes and builds on the results of previous ARTEMIS, European and National projects. It provides the paradigm shift to a new and sustainable system architecture which is suitable to handle open dynamic systems. EMC is part of the European Embedded Systems industry strategy to maintain its leading edge position by providing solutions for: . Dynamic Adaptability in Open Systems . Utilization of expensive system features only as Service-on-Demand in order to reduce the overall system cost. . Handling of mixed criticality applications under real-time conditions . Scalability and utmost flexibility . Full scale deployment and management of integrated tool chains, through the entire lifecycle Approved by ARTEMIS-JU on 12/12/2013 for EoN. Minor mistakes and typos corrected by the Coordinator, finally approved by ARTEMIS-JU on 24/01/2014. Amendment 1 changes approved by ECSEL-JU on 31/03/2015.


Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2011.3.3 | Award Amount: 3.69M | Year: 2011

For a few years, multiprocessors have penetrated the embedded market. Platform providers such as Texas Instrument, STMicroelectronics or ST-Ericsson now propose multicore architectures with scalable performances. These architectures are capable to cope with the rising processing needs, while keeping stable power consumption. They provide developers with more flexibility and offer efficient power monitoring and control features. These evolutions will therefore help to sustain the market growth, but at the expense of programmability.\n\nHardware architectures evolve faster than software tools, and the specification and mapping of applications onto new heterogeneous multicore architectures becomes more complex. The lack of efficient software tools hinders adoption of new architectures and increases software development costs. The European industry therefore has to face a new challenge and sustain software developments by introducing efficient tools capable to assist designers.\n\nThe main objective of PHARAON is to improve competitiveness of the European electronic industry, especially with respect to reducing power consumption and improving performance, by providing new paradigms for multicore architectures programming, monitoring and control, as well as new dynamic power adaptation strategies, algorithms and interfacing standards. Raising the expertise of European industry in system architecture, software development and power management is crucial to ease the transition to multicore platforms. It will enlarge the range of applicability of a hardware platform and plays in favour of re-use, cost and time-to-market reduction, which have become crucial requirements in a worldwide competition.


Grant
Agency: European Commission | Branch: FP7 | Program: JTI-CP-ARTEMIS | Phase: SP1-JTI-ARTEMIS-2013-ASP5 | Award Amount: 16.68M | Year: 2014

ALMARVI aims at providing cross-domain many-core platform solution, system software stack, tool chain, and adaptive algorithms that will enable massive data-rate image/video processing with high energy efficiency. ALMARVI will provide mechanisms and support for high degree of adaptivity at various system layers that will abstract the variations in the underlying platforms (e.g., due to imperfections in the fabrication process), communication channels (e.g., available bandwidth), application behaviour (dynamic workloads, changing requirements) from the application developer. This is crucial for providing consistent performance efficiency in an interoperable manner when considering heterogeneous platform options and dynamic operating conditions. The key is to leverage image/video content-specific properties, application-specific features, and inherent resilience properties of image/video processing applications. The goal of ALMARVI is to develop: Adaptive, scalable, and parallelised algorithms for image and video processing Cross-domain system software stack with adaptive run-time system for efficient resource/power management and improved interoperability Concepts for continuous hardware and software adaptations Cross-domain many-core execution platform scalable with off-the-shelf heterogeneous acceleration fabrics like FPGAs, embedded GPUs, DSPs, etc. Design tools and methods for execution platform Industrial-grade demonstrators for multiple application use cases to validate the project results. APPROVED by ARTEMIS-JU 03/07/2015 (amendment nr 1)


Holdermans S.,Vector Fabrics
Proceedings of the 15th Symposium on Principles and Practice of Declarative Programming, PPDP 2013 | Year: 2013

Algebraic specification, equational reasoning, and property-based random testing provide functional programmers with a powerful yet reasonably lightweight framework for reasoning about abstract datatypes and assuring the quality of their concrete implementations. However, as it turns out, naïvely implementing property-based random testing for purely functional abstract datatypes is prone to subtle errors and may well leave unaware practitioners with a false sense of security about their datatype implementations. In this paper, we pinpoint one particular pitfall, namely overlooking the need to take into account the invariance of datatype operations under an implied equivalence relation on concreate datatype values, and discuss how to systematically avoid it. Presented in the context of a concrete case study, the proposed technique generalises nicely into a common design principle for engineering random tests of purely functional datastructures. © 2013 ACM.


Patent
Vector Fabrics | Date: 2015-07-13

A computer-implemented method of automatically generating an embedded system on the basis of an original computer program, comprising analyzing the original computer program, comprising a step of compiling the original computer program into an executable to obtain data flow graphs with static data dependencies and a step of executing the executable using test data to provide dynamic data dependencies as communication patterns between load and store operations of the original computer program, and a step of transforming the original computer program into an intermediary computer program that exhibits multi-threaded parallelism with inter-thread communication, which comprises identifying at least one static and/or dynamic data dependency that crosses a thread boundary and converting said data dependency into a buffered communication channel with read/write access.


Patent
Vector Fabrics | Date: 2010-06-01

A computer-implemented method of automatically generating an embedded system on the basis of an original computer program, comprising analyzing the original computer program, comprising a step of compiling the original computer program into an executable to obtain data flow graphs with static data dependencies and a step of executing the executable using test data to provide dynamic data dependencies as communication patterns between load and store operations of the original computer program, and a step of transforming the original computer program into an intermediary computer program that exhibits multi-threaded parallelism with inter-thread communication, which comprises identifying at least one static and/or dynamic data dependency that crosses a thread boundary and converting said data dependency into a buffered communication channel with read/write access.


Patent
Vector Fabrics | Date: 2013-05-28

Method and system for translating a function in a computer programming language into a non-native instruction set, as part of a program that is otherwise in a native instruction set computer program. The method comprises translating the function into the non-native instruction set, prefixing the translated function with a preamble in the native instruction set format that implements the required conversion and non-native instruction set interpretation when called from native code segments, and incorporating into the translated function and/or the preamble a means of identifying the function as being in the non-native instruction set.


Patent
Vector Fabrics | Date: 2011-04-04

A method of generating an embedded system (4999) from an original computer program (996) which embedded system (4999) provides a parallellized hardware (4598) and software (4599) implementation of the original computer program (996), which parallellized implementation (4598, 4599) satisfies one or more criteria regarding hardware constraints of the embedded system (4999). The system provides partitioning of functionality from the original computer program (996) using structural and behavioral program models and detects streaming and memory dependencies to improve the partitioning, relying on added indications of source lines and variables in said original computer program to relate partitions and dependencies in the program model with locations in the original program source code.

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