Vanguard International Semiconductor Corporation

Hsinchu, Taiwan

Vanguard International Semiconductor Corporation

Hsinchu, Taiwan
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Patent
Vanguard International Semiconductor Corporation | Date: 2016-01-07

A low dropout regulator is provided. The low dropout regulator includes an output-stage circuit, a reference-voltage generation circuit, a timing controller, and an active low dropout circuit. When the low dropout regulator is at an operation mode, the output-stage circuit is controlled by a first enable signal to generate first output voltage to an output node of the low dropout regulator. The reference-voltage generation circuit is controlled by a bias voltage to generate a first reference voltage. The timing controller is coupled to the output node and receives the first reference voltage. When the low dropout regulator is in the operation mode, the timing controller programs the first enable signal according to the reference voltage and the voltage at the output node. When the low dropout regulator is in a standby mode, the active low dropout circuit generates a second output voltage to the output node.


Patent
Vanguard International Semiconductor Corporation | Date: 2017-02-10

A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.


Patent
Vanguard International Semiconductor Corporation | Date: 2015-12-28

A high-side circuit, adapted for a switched-mode converter, includes a level shifter, a high-side driver, a high-side transistor, a capacitor, and an active diode. The level shifter receives a first signal to generate a set signal. The high-side driver is supplied by a bootstrap voltage of a bootstrap node and a floating reference voltage of a floating reference node, which controls the high-side transistor to provide an input voltage to the floating reference node according to the set signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides a supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node according to a control voltage. The active diode includes a first-type well coupled to the bootstrap node, where the high-side driver is disposed.


Patent
Vanguard International Semiconductor Corporation | Date: 2015-12-02

A switch-mode converter includes a high-side driver, a high-side transistor, a low-side driver, a low-side transistor, a capacitor, and an active diode. The high-side driver is supplied by the bootstrap voltage of the bootstrap node and a floating reference voltage of a floating reference node, and generates the high-side output signal. The high-side transistor provides an input voltage to the floating reference node according to the high-side output signal. The low-side driver generates the low-side output signal. The low-side transistor couples the floating reference node to a ground according to the low-side output signal. The capacitor is coupled between the bootstrap node and the floating reference node. The active diode provides the supply voltage to the bootstrap node. When the bootstrap voltage exceeds the supply voltage, the active diode isolates the supply voltage from the bootstrap node.


Patent
Vanguard International Semiconductor Corporation | Date: 2015-09-09

The invention provides a semiconductor device layout structure disposed in an active region. The semiconductor device layout structure includes a first well region having a first conduction type. A second well region having a second conduction type opposite the first conduction type is disposed adjacent to and enclosing the first well region. A first doped region having the second conduction type is disposed within the first well region. A second doped region having the second conduction type is disposed within the first well region. The second doped region is separated from and surrounds the first doped region. A third doped region having the second conduction type is disposed within the second well region.


Patent
Vanguard International Semiconductor Corporation | Date: 2016-12-13

A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.


Patent
Vanguard International Semiconductor Corporation | Date: 2016-02-24

A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.


Patent
Vanguard International Semiconductor Corporation | Date: 2016-06-22

A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction.


Patent
Vanguard International Semiconductor Corporation | Date: 2016-03-16

A semiconductor device includes: a plurality of stacked semiconductor layers; a plurality of composite doped regions separately and parallelly disposed in a portion of the semiconductor layers along a first direction; a gate structure disposed over a portion of the semiconductor layers along a second direction, wherein the gate structure covers a portion of the composite doped regions; a first doped region formed in the most top semiconductor layer along the second direction and being adjacent to a first side of the gate structure; and a second doped region formed in the most top semiconductor layer along the second direction and being adjacent to a second side of the gate structure opposite to the first side thereof.


Patent
Vanguard International Semiconductor Corporation | Date: 2016-01-27

A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

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