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Hoang T.-T.,The University of Science | Su H.-K.,The University of Science | Nguyen H.-B.,The University of Science | Le D.-H.,The University of Science | And 3 more authors.
IEICE Electronics Express | Year: 2015

Although HMM-based TTS has been studied for many years, there are some limitations such as real-time applications based on lowperformance and low cost systems. In this paper, we present a design of a TTS co-processor used for HMM-based Text-to-Speech (TTS) hardware systems. Based on a dedicated FPU and resource sharing architecture, the coprocessor can compute a lot of DSP algorithms required by HMM at very high speed. The system has been built and verified on the FPGA system with English and Vietnamese languages. The results show that it can compute up to 3 words per second at frequency of 100MHz with the resources cost about 32,000 logic elements, 19,000 registers, and 957KB memory. © IEICE 2015. Source

Nguyen H.-T.,University of Electro - Communications | Nguyen X.-T.,University of Electro - Communications | Hoang T.-T.,The University of Science | Le D.-H.,The University of Science | Pham C.-K.,University of Electro - Communications
IEICE Electronics Express | Year: 2015

Despite being proposed since more than 50 years ago, COordinate Rotation DIgital Computer (CORDIC) is still one of the most effective algorithms for elementary function calculation so far. Original CORDIC, however, suffers high latency due to its nature of unvarying number of rotations. As a result, a low-latency hybrid adaptive (HA) CORDIC is proposed in this paper. Firstly, adaptive angle selection decreases total iterations up to 50% with respect to higher accuracy of results. Secondly, hybrid architecture including fixed-point input and floating-point output reduces the total hardware utilization and enhances the dynamic range of final results. Lastly, parallel and pipeline processing together with resource sharing technique allow the design to operate fully at 175.7MHz with low resource consumption—1,139 LUTs and 489 registers. © IEICE 2015. Source

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