United Test and Assembly Center

Singapore, Singapore

United Test and Assembly Center

Singapore, Singapore
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Tamil J.,United Test and Assembly Center | Ore S.H.,United Test and Assembly Center | Gan K.Y.,United Test and Assembly Center | Koh D.,United Test and Assembly Center | And 8 more authors.
Journal of Microelectronics and Electronic Packaging | Year: 2012

Moldability is a crucial aspect of flip chip technology. It is an increasing challenge to ensure moldability with rapid advances in flip chip technology such as decreasing bump pitch and stand-off height, especially when commercial molded underfill (MUF) is used and, in particular, during panel level molding. One key challenge faced is severe void entrapment beneath the die. Typically, large DOE matrix experiments are used to address this issue, which require significant time and process resources. 3D flow simulation can be used to optimize the process to reduce defects with a smaller number of actual runs. By correlating theoretical and experimental phenomena, flow simulation enhances the understanding of the complex fluid dynamics during the molding process. 3D flow simulation can assist in widening the process window, which is limited by the inherent machine and material challenges. This can be achieved by prediction of the effect of varying design, material, and process parameters on melt front behavior and void locations. 3D mold flow simulation using Moldex3D V10 is used to optimize the MUF transfer molding on selected flip chip devices. This paper proposes and verifies a systematic flow simulation methodology designed to save computational resources by using a three step analysis. The initial step, simplified panel level simulation, is to optimize the process parameters to obtain a balanced melt front Next, on the package level, we studied the effect of various parameters. This analysis provides a prediction of the void location and an insight into the appropriate parameters to minimize the void problem. The optimized parameters from the preliminary simulation were used as guidelines. For the second step, a full validation was conducted. A complete full panel-level flow model was built, where the process and design parameters adopted in the actual molding were implemented. The actual void location and size from the experiment were captured by scanning acoustic microscope (SAM) machine and parallel lapping (p-lapping). Short shots were also obtained to study the melt front behavior. The panel mold filling simulations showed good correlation with the experimental short shots and actual void locations. The prediction capability is further enhanced by zooming in to the column level, and this enhanced model was able to predict the other lower risk voids away from the main problem areas. This was correlated with actual CSAM data and p-lapping. The 3D flow simulation enhances the understanding of causes of flow imbalance, void signature, void formation, and the effect of varying bump height, die thickness, mold cap thickness, gate height, die orientation, transfer profile, and mold temperature as potential enhancement measures. With a successful correlation between simulation and process data as shown in this paper, we have demonstrated that mold flow simulation is a reliable tool to effectively reduce the design-to-implementation cycle time, identifying potential key problems during actual fabrication and potential solutions to reduce defects.


Tamil J.,United Test and Assembly Center | Ore S.H.,United Test and Assembly Center | Gan K.Y.,United Test and Assembly Center | Bo Y.Y.,United Test and Assembly Center | And 4 more authors.
44th International Symposium on Microelectronics 2011, IMAPS 2011 | Year: 2011

Increasing challenges are faced to ensure moldability with rapid advances in flip chip technology such as decreasing bump pitch and stand-off height, especially when commercial Moldable Underfill (MUF) is used and in particular, during panel level molding. One key challenge faced is severe void entrapment under the die. Experiments involving a large DOE matrix, which require significant time and process resources, are typically used to solve this issue. 3D flow simulation can be used to optimize the process to reduce defects without doing actual runs. Mold flow simulation can effectively reduce the design-to-implementation cycle time, identifying key problems before actual fabrication. In this paper, 3D mold flow simulation using Moldex3DTM V10 is applied to transfer molding to optimize design and process parameters. This paper proposes and verifies a systematic method that can save computational resources by using 2 steps analysis: simplified panel simulation and single package simulation. The initial step, simplified panel level simulation, is to optimize the process parameters to obtain balanced melt front. The second step is to study on the package level the effect of various package-scale parameters. This analysis provides a prediction of the void location and an insight on the appropriate parameters to minimize void problem. The actual voids location and size from the experiment was captured by SAT machine and short shots were obtained. For final validation, a complete panel-level flow model is built, where the process and design parameters adopted in the actual molding were implemented. The mold filling simulation showed good correlation with the experimental short shots and actual void location. With optimized parameters from the simulation used as guidelines, experimental tests were conducted and the study showed that the simulation is a useful tool to optimize the molding process.


Yang Y.B.,United Test and Assembly Center | Kumar N.,WorleyParsons Group Inc | John D.,United Test and Assembly Center | Hyman R.,United Test and Assembly Center | And 3 more authors.
Proceedings of the 2012 IEEE 14th Electronics Packaging Technology Conference, EPTC 2012 | Year: 2012

In recent years, many OSAT (Outsourced Semiconductor Assembly and Test) companies start to explore copper wire bond process, which is believed to be able to reduce the IC packaging cost. Copper wire also shows better electrical performance especially for fine wire. However, the reliability maintenance is not as easy as gold wire. Some companies encountered numerous problems in mass production although the copper wire is qualified in engineering stage. This paper is an attempt to understand the bond pad design impact on pad stress as well as the low K layer stress. In this paper, an axisymmetric transient nonlinear dynamic finite element analysis is developed to assist the understanding of copper wire bond process. In the modeling, only Aluminum pad and low-K layers of the bond pad structure are focused. 4 bond pad structures are selected for the stress comparison from Aluminum pad surface to chip low-K layer. Firstly, the stress on Al pad and low K layer is studied with our standard capillary design and bond pad at different stage. Then the capillary inner chamfer angle is varied from 50° to 120 ° to see the impact. Lastly, 4 bond pad structures are presented for comparison. © 2012 IEEE.


Ore S.H.,United Test and Assembly Center | Zhu W.H.,Tian Shui Hua Tian Technology Co. | Yuan W.L.,United Test and Assembly Center | Suthiwongsunthorn N.,United Test and Assembly Center
Proceedings - 2010 11th International Conference on Electronic Packaging Technology and High Density Packaging, ICEPT-HDP 2010 | Year: 2010

Due to rising thermal concerns from increasing power densities and industry demands for shorter development cycle times, we have developed quick solutions to assess the thermal performance of the FBGA package, one of the most widespread package options. We have designed a user friendly tool that provides a quick estimation of the junction to ambient thermal resistance of the FBGA package under JEDEC test conditions (JESD 51-2 and JESD 51-6). Results can be obtained within minutes by a click of a button after the simple entry of key package and environmental data. The tool significantly reduces the time for thermal evaluation; from hours or days needed to conduct full Computational Fluid Dynamics (CFD) simulations, to minutes by using the tool. It can also be used for upfront thermal design as it is able to assess the thermal impact due to changes in various package factors such as package size, die size, presence of solder balls under the die area, number and thickness of substrate metallized layers, total substrate thickness and number of thermal vias under the die area. The tool is also able to assess the impact due to changes in wind speed up to 1m/s and test board including both the 1S0P and 2S2P JEDEC PCB. With these features, the tool can be used to quickly estimate if the package specifications meet the desired thermal requirement, and if it fails to meet the requirement, rapidly identify potential package thermal design options. The formulation of the tool was challenging due to large number of factors involved such as the individual package components, environmental parameters and test boards. The complexity was further exacerbated by the complicated interactions between these factors and their impact on thermal performance. A systematic approach was thus designed to tackle these challenges. The formulation begun by the analysis of a large database of CFD simulation studies that were conducted for FBGA production devices. Using Design of Experiments (DOE), additional identified CFD simulations were conducted for a comprehensive assessment of all the factors. Experimental measurements were conducted using selected FBGA production devices under JEDEC still air and forced convection conditions on both 1S0P and 2S2P test boards. CFD simulation results of the selected test vehicles shows excellent agreement with the experimental studies with less than 10% deviations. From the extensive list of package and environmental parameters, key factors with significant thermal impact were identified through DOE and analysis of customized partial factorial results. It is found that the package size, die size, presence of solder balls under the die area and the substrate thermal conductivity are the key package factors with significant impact on the FBGA thermal performance. The FBGA thermal performance was then expressed as a function of these factors. Next, to verify that the key trends are well captured, the tool was then subjected to rigorous testing by comparison with both Computational Fluid Dynamics (CFD) simulation results and experimental measurements. Comparison of results shows that the discrepancies are within 15% under a specified applicable range, with more than 75% of the test results having less than 10% deviations. This paper presents the approach used in the formulation of the tool and the valuable insights on the FBGA package structure and thermal performance thus obtained. © 2010 IEEE.


Lau J.H.,Industrial Technology Research Institute of Taiwan | Yue T.G.,United Test and Assembly Center
Microelectronics Reliability | Year: 2012

Thermal performances of 3D IC integration system-in-package (SiP) with TSV (through silicon via) interposer/chip are investigated based on heat-transfer and CFD (computational fluid dynamic) analyses. Emphases are placed on the determination of (1) the equivalent thermal conductivity of interposers/chips with various copper-filled, aluminum-filled, and polymer w/o filler filled TSV diameters, pitches, and aspect ratios, (2) the junction temperature and thermal resistance of 3D IC SiP with various TSV interposers, (3) the junction temperature and thermal resistance of 3D stacking of up to 8 TSV memory chips, and (4) the effect of thickness of the TSV chip on its hot spot temperature. Useful design charts and guidelines are provided for engineering practice convenient. © 2012 Elsevier Ltd. All rights reserved.


Yang Y.B.,United Test and Assembly Center | Zhang X.R.,United Test and Assembly Center | Zhu W.H.,Tian Shui Hua Tian Technology Co. | Teddy J.C.,United Test and Assembly Center | And 3 more authors.
Proceedings - 2010 11th International Conference on Electronic Packaging Technology and High Density Packaging, ICEPT-HDP 2010 | Year: 2010

This paper focused on the delamination study of low profile leadframe package with exposed pad (eLQFP). In this type of package, a specification of silver plating area is required for bond pad. With the shrinkage of the non-plating pad area, and because of low adhesion strength between silver and mold compound, the interface of mold compound and diepad in the silver plating area may potentially delaminate especially after moisture sensitivity level 3 test (MSL3) and IR reflow. The study is to define a design guideline and mold compound selection rule for minimum delamination after MSL3 & IR reflow. Firstly, a safety factor K is defined as delamination guideline. Then the structure parameters were prioritized for their impact to the factor K. Thirdly, a DOE was carried out to study the mold compound property effect on the delamination. Guided by the simulation in structure and mold compound study, a group of test vehicles were designed to validate the reliability. The result shows the well-defined safety factor K was workable for eLQFP failure evaluation. © 2010 IEEE.


Smith L.,United Test and Assembly Center | Goodman T.,Izinus Technologies
Advancing Microelectronics | Year: 2015

Internet of Things (IoT) was explored in the IMAPS Global Business Council's half-day plenary session March 18, 2015. Bill McClean, President of IC Insights, provided a keynote talk on the 'IC Market in an Unstable Economy.' Bill forecasts the electronic systems market to grow 6% approaching $1.6 trillion in 2015, which is about 2% of the global gross domestic product (GDP) and the semiconductor market to grow 7% to $378 billion. Stephen Whalley, Chief Strategy Officer, MEMS Industry Group (MIG) provided the second talk on 'Maximizing the Internet of Everything by Mobilizing the MEMS/Sensors and Adjacent Ecosystems'. Mike Stanley, Manager, Systems / Algorithms, Sensor Solutions Division of Freescale Semiconductor, spoke on 'Evolving Challenges for Sensor/MEMS Packaging.' Mike's talk transitioned from the market outlook and industry association role to a focus on the sensor and packaging technologies required to enable the smart devices connected to IoT networks. E. Jan Vardaman, President of TechSearch International, was the fourth GBC speaker providing a summary of 'The Wearable Market and Packaging Requirements.' Rozalia Beica, Chief Technology Officer of Yole D?veloppement, provided an overall business perspective with her talk on 'Market Trends and Evolution of IoT.'


Ore S.H.,United Test and Assembly Center | Edith Poh S.W.,United Test and Assembly Center | Zhu W.H.,Tian Shui Hua Tian Technology Co. | Yuan W.L.,United Test and Assembly Center | Suthiwongsunthorn N.,United Test and Assembly Center
Proceedings - 2010 11th International Conference on Electronic Packaging Technology and High Density Packaging, ICEPT-HDP 2010 | Year: 2010

This paper presents the results of thermal performance and mechanical reliability co-design of flip chip devices by a comprehensive evaluation of package structure and material effects. The study provided valuable insights that can assist to identify potential package solutions and enhancement options by considering process, materials, thermal performance and mechanical reliability. With concurrent thermal and mechanical analysis, the thermal trends obtained from this study can be used to enhance the selection of thermal options and the reliability insights gained allowed further mechanical optimizations to identified solutions. The study evaluates both the larger sized FC-BGA and smaller sized FC-CSP using selected production, development and potential devices. A total of 6 FC-BGA and 5 FC-CSP test vehicles were selected for the study. The UTAC-patented XP (eXtra Performance) embedded heat spreader was also assessed and benchmarked against the other test vehicles. Thermal performance analysis, detailed package level stress and warpage analysis were conducted for all the identified test vehicles. For both FC-BGA and FC-CSP devices, analysis results showed that the bare die structure has the highest warpage and highest junction-to-ambient thermal resistance. The addition of mold compound is able to improve warpage for small die FC-BGA packages. However, mold compound results in insignificant warpage improvements when die-topackage ratio is large, such as in the FC-CSP. Concurrent thermal analysis shows that mold compound slightly enhances the thermal performance of both FC-BGA and FC-CSP devices under no/low wind velocities. Heat spreaders or heat sinks are comparatively more effective thermal enhancement solutions. The effects of heat spreaders were analyzed using several different package structures. Other than the thermal benefits reaped, heat spreaders brought about significant warpage control. Especially in the case of XP, the combined effect of the mold compound and the embedded heat spreader remarkably reduced warpage even in package with large dieto-package ratio. However, stress analysis showed a 10-25%increase in die stress for both small and large die packages when the heat spreader is used. With the recent interest and migration to the use of moldable underfill material (MUF), its performance was also enchmarked against the conventional capillary underfill (CUF) and mold compound. Thermal analysis results shows that MUF results in minor thermal enhancements compared to the capillary underfill (CUF). Mechanical analysis results showed that the MUF improves package coplanarity when the package exhibited smiling warpage behaviour at room temperature. The shift in critical die and underfill stresses was also observed with the change in material set The thermal performance and mechanical reliability costudy adopted a holistic approach that obtained the trends and insights learnt that enabled informed choices to be made in materials selection and identification of potential packages. The approach and the insights obtained are thus presented in this paper. © 2010 IEEE.


Patent
United Test And Assembly Center | Date: 2011-02-23

A method of forming a device is disclosed. The method includes providing a printed circuit board substrate having a die attach region on a first surface of the substrate. The method also includes attaching a die to a die attach region. The die is electrically coupled to first land pads disposed on the first surface at the periphery of the die attach region. A cap is formed in a target area by a top gate process to produce a cap with an even surface. The cap covers the die and leaves at least the first land pads exposed.

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