United Silicon Carbide, Inc. | Date: 2017-01-13
A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.
United Silicon Carbide, Inc. | Date: 2016-10-25
A silicon surge bypass diode is co-packaged with a high bandgap junction barrier Schottky diode. The co-packaged diodes may be used in a power circuits such as power factor correction circuits, converters, inverters circuit, motor drives, and protection circuits, for example. The high bandgap diode may be made of silicon carbide, gallium nitride, aluminum nitride, aluminum gallium nitride, and/or diamond, for example. The high bandgap diode may be formed by diode connecting a transistor, such as a high-electron-mobility transistor (HEMT). The high bandgap diode may be much smaller than the silicon diode. The package may have a common terminal for the diode cathodes, and separate terminals for the anodes of each diode.
United Silicon Carbide, Inc. | Date: 2016-09-16
A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.
United Silicon Carbide, Inc. | Date: 2017-03-01
Systems and methods for semiconductor wafer processing include irradiating a surface of a semiconductor wafer with a laser beam of sufficient energy to alter a band gap of semiconductor material thereby melting a portion of the wafer to generate a graphitic layer area. A metal layer is then depositing on the surface to create ohmic contacts at the area that where melted by the laser.
United Silicon Carbide, Inc. | Date: 2017-04-05
Disclosed herein are cascode switching circuits that include a normally-on semiconductor device, a normally-off semiconductor device, and a gate driver. The normally-on semiconductor device and said normally-off semiconductor device each has a gate terminal, a drain terminal and a source terminal. The gate driver has a first output and a second output, the first output of said gate driver is coupled to said gate terminal of said normally-on semiconductor device, the second output of said gate driver is coupled to said gate terminal of said normally-off semiconductor device, and the drain terminal of said normally-off semiconductor device is coupled to said source terminal of said normally-on semiconductor device so that a current path is formed through said normally-on semiconductor device and said normally-off semiconductor device. Methods of making and using such circuits, and other various aspects of such circuits are also disclosed.
United Silicon Carbide, Inc. | Date: 2016-09-15
A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A maskless self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.
Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 154.60K | Year: 2016
In 2014, approximately ~120,000 plug-in electric vehicles (PEV’s) were sold in the US alone, representing a 23% increase from 2013 and a 128% increase from 2012 and nearly 1/3 of the PEV’s sold worldwide, making the US the largest market for PEV and HEV adoption. It is expected that by 2023, there will be ~3.2 million PEV’s on the road in the U.S. alone. The EV Everywhere initiative has set the goal to make electric vehicles as affordable as gasoline vehicles by 2022. To meet the goals of the EV Everywhere initiative, the primary efforts lie in reducing costs for the batteries, PM motor and electric drive train while simultaneously reducing weight. Increasing the drive train conversion efficiency has a significant impact as it extends battery life, vehicle range and allows for a reduction of heavy cooling components through the reduction of heat generating losses. Therefore much attention is placed on increasing the efficiency of the traction power inverter that drives the electric motor. It is well documented that inverter efficiency and power density can be increased while simultaneously reducing weight through the use of Silicon Carbide (SiC) wide bandgap semiconductors. For example, demonstrations of inverters utilizing SiC-JFETs and SiC-MOSFETs are emerging, where the efficiencies are reaching >99% with 10X increased power densities. However, today’s electric vehicle motor drive applications require high current (200-400A) power modules. SiC devices have been limited to lower current (
Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 1.01M | Year: 2016
The U.S. represents the world’s leading market for electric vehicles and is producing some of the most advanced plugin electric vehicles (PEV’s) available today. PEV’s are gaining widespread adoption every year, where 58% of all PEV sales occurred in 2013 and it is expected that by 2023, there will be ~3.2 million PEV’s on the road in the U.S. alone. To increase adoption and maintain this leadership, the EV Everywhere initiative has set the goal to make electric vehicles as affordable as gasoline vehicles by 2022. To meet the goals of the EV Everywhere initiative, the primary efforts lie in reducing costs
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 749.64K | Year: 2016
Radiation tolerant, extreme temperature capable electronics are needed for a variety of planned NASA missions. For example, in-situ exploration of Venus and long duration Europa-Jupiter missions will expose electronics to temperatures up to 500 ?C and radiation of 3 Mrad (Si) total dose. During this program, United Silicon Carbide will extend the capability of its SiC JFET integrated circuit (IC) fabrication technology to produce electronics compatible with such extreme environments. Silicon Carbide (SiC) junction field effect (JFET) based electronics are ideal for these environments due to their radiation tolerance and their high performance and reliability over an extremely wide operating temperature range. SiC electronics can be used in applications ranging from low power, low noise mixed signal electronics for precision actuator control, sensor interfaces, and guidance and navigation electronics to power electronics for power management and distribution and power processing units. SiC based electronics will have longer storage and operating lifetimes when compared to existing silicon electronics. Use of SiC integrated circuits will also lower system mass, volume, and power by reducing or eliminating the need for cooling and radiation shielding. In Phase I, we showed the feasibility of our approach by measuring SiC JFET IC device characteristics at 500 ?C; performing a 500 hour, 500 ?C reliability test; and using TCAD simulations to further explore the devices behavior at high temperature and when subjected to radiation. In Phase II, we will fully develop the extreme environment capable SiC IC fabrication technology and use it to fabricate an integrated circuit which will be characterized at 500 ?C and before and after radiation exposure. Following Phase II, we will provide access to the process technology and related design intellectual property through a commercial fabrication service so that NASA and others can fully leverage its capability.
United Silicon Carbide, Inc. | Date: 2016-09-09
Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. The etching goes through the source layer and partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions.