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Pagano G.,French Institute for Research in Computer Science and Automation | Marangozova-Martin V.,UJF
EICS 2014 - Proceedings of the 2014 ACM SIGCHI Symposium on Engineering Interactive Computing Systems | Year: 2014

Trace analysis graphical user environments have to provide different views on trace data, in order to be effective in helping the comprehension of the traced application behavior. In this article we propose an open and modular software architecture, the FrameSoC workbench1, which defines clear principles for view engineering and for view consistency management. The FrameSoC workbench has been successfully applied in real trace analysis use cases. Copyright © 2014 ACM 978-1-4503-2725-1/14/06. Source

Gindraud F.,UJF | Rastello F.,French Institute for Research in Computer Science and Automation | Cohen A.,French Institute for Research in Computer Science and Automation | Broquedis F.,Grenoble Institute of Technology
International Symposium on Memory Management, ISMM | Year: 2016

This paper presents a memory allocator targeting manycore architectures with distributed memory. Among the family of Multi Processor System on Chip (MPSoC), these devices are composed of multiple nodes linked by an on-chip network; most nodes have multiple processors sharing a small local memory. While MPSoC typically excel on their performance-per-Watt ratio, they remain hard to program due to multilevel parallelism, explicit resource and memory management, and hardware constraints (limited memory, network topology). Typical programming frameworks for MPSoC leave much targetspecific work to the programmer: combining threads or nodelocal OpenMP, software caching, explicit message passing (and sometimes, routing), with non-standard interfaces. More abstract, automatic frameworks exist, but they target large-scale clusters and do not model the hardware constraints of MPSoC. The memory allocator described in this paper is one component of a larger runtime system, called Givy, to support dynamic task graphs with automatic software caching and data-driven execution on MPSoC. To simplify the programmer's view of memory, both runtime and program data objects live in a Global Address Space (GAS). To avoid address collisions when objects are dynamically allocated, and to manage virtual memory mappings across nodes, a GAS-aware memory allocator is required. This paper proposes such an allocator with the following properties: (1) it is free of inter-node synchronizations; (2) its node-local performance match that of state-of-the-art shared-memory allocators; (3) it provides node-local mechanisms to implement inter-node software caching within a GAS; (4) it is well suited for small memory systems (a few MB per node). © 2016 ACM. Source

Yguel M.,French Institute for Research in Computer Science and Automation | Vasquez D.,ETH Zurich | Aycard O.,UJF | Siegwart R.,ETH Zurich | Laugier C.,French Institute for Research in Computer Science and Automation
Springer Tracts in Advanced Robotics | Year: 2011

The accuracy of Grid-based maps can be enhanced by putting a Gaussian in every cell of the map. However, this solution works poorly for coarse discretizations in multi-scale maps. This paper proposes a method to overcome the problem by allowing several Gaussians per cell at coarse scales. We introduce a multi-scale approach to compute an error measure for each scale with respect to the finer one. This measure constitutes the basis of an incremental refinement algorithm where the error is used to select the cells in which the number of Gaussians should be increased. As a result, the accuracy of the map can be selectively enhanced by making efficient use of computational resources. Moreover, the error measure can also be applied to compress a map by deleting the finer scale clusters when the error in the coarse ones is low. The approach is based on a recent clustering algorithm that models input data as Gaussians rather than points, as is the case for conventional algorithms. In addition to mapping, this clustering paradigm makes it possible to perform map merging and to represent feature hierarchies under a sound theoretical framework. Our approach has been validated with both real and simulated 3-D data. © 2011 Springer-Verlag. Source

Jecu C.,Schneider Electric | Alibert P.,Schneider Electric | Raison B.,UJF | Caire R.,Grenoble Institute of Technology | And 2 more authors.
IET Conference Publications | Year: 2013

This work is related to protection systems on MV distribution networks. Most of these grids are currently protected by a single relay on the beginning of each feeder. The Smart Grids necessity is becoming more and more a reality for the grids of tomorrow. These more complex grids with Distributed Generation (DG) interconnection could require a more complex protection system to achieve high quality service and enhance the grid stability. This work proposes non communicating, distributed distance relays. These deployed relays would divide the feeder in smaller protected areas leading to shorter outage occurrence and duration for loads and producers. The proposed method was tested on all types of grids with overhead lines, cables and mixed, for all several different neutral groundings of the HV/MV transformer with or without DG presence. This method is subject to a patent deposition in 2012. Source

Dashti M.,Simon Fraser University | Fedorova A.,Simon Fraser University | Funston J.,Simon Fraser University | Gaud F.,Simon Fraser University | And 4 more authors.
International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS | Year: 2013

NUMA systems are characterized by Non-Uniform Memory Access times, where accessing data in a remote node takes longer than a local access. NUMA hardware has been built since the late 80's, and the operating systems designed for it were optimized for access locality. They co-located memory pages with the threads that accessed them, so as to avoid the cost of remote accesses. Contrary to older systems, modern NUMA hardware has much smaller remote wire delays, and so remote access costs per se are not the main concern for performance, as we discovered in this work. Instead, congestion on memory controllers and interconnects, caused by memory traffic from data-intensive applications, hurts performance a lot more. Because of that, memory placement algorithms must be redesigned to target traffic congestion. This requires an arsenal of techniques that go beyond optimizing locality. In this paper we describe Carrefour, an algorithm that addresses this goal. We implemented Carrefour in Linux and obtained performance improvements of up to 3.6 relative to the default kernel, as well as significant improvements compared to NUMA-aware patchsets available for Linux. Carrefour never hurts performance by more than 4% when memory placement cannot be improved. We present the design of Carrefour, the challenges of implementing it on modern hardware, and draw insights about hardware support that would help optimize system software on future NUMA systems. Copyright © 2013 ACM. Source

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