Neu-Ulm, Germany
Neu-Ulm, Germany

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Karthaus U.,Ubidyne GmbH | Sukumaran D.,Ubidyne GmbH | Schmidt L.,Ubidyne GmbH | Ahles S.,Ubidyne GmbH | Wagner H.,Ubidyne GmbH
European Microwave Week 2012: "Space for Microwaves", EuMW 2012, Conference Proceedings - 7th European Microwave Integrated Circuits Conference, EuMIC 2012 | Year: 2012

After providing an introduction to active antenna systems (AAS) for cellular infrastructure, this paper presents power amplifier (PA) modules based on a balanced configuration of 2-8 fully integrated Doherty MMIC PAs. To our knowledge for the first time, a module with four Doherty MMIC PAs in a balanced configuration has been fabricated and tested. For a 10 MHz wide LTE downlink signal at 751 MHz, average and peak output power levels were 37.8 dBm and 45.0 dBm, respectively, with ACPR ≤-48.5 dBc. Overall PAE was 34 %. © 2012 European Microwave Assoc.


Karthaus U.,Ubidyne GmbH | Ahles S.,Ubidyne GmbH | Elmaghraby A.,Ubidyne GmbH | Wagner H.,Ubidyne GmbH
European Microwave Week 2012: "Space for Microwaves", EuMW 2012, Conference Proceedings - 7th European Microwave Integrated Circuits Conference, EuMIC 2012 | Year: 2012

This paper presents a radio frequency (RF) continuous-time band-pass delta sigma modulator (CT BP DSM) receiver realized in a 180 nm SiGe BiCMOS technology. The internal quantizer and feedback DAC resolution is 2 bit. Without applying DAC linearization techniques such as trimming or dynamic element matching, measured performance parameters include an SNR and SNDR in 35 MHz of 56.7 dB and 53.7 dB, respectively. Image rejection across the notch center at a quarter of the clock frequency is at least 76 dB. IIP3 and noise figure are -6.6 dBm and 10 dB, respectively. © 2012 European Microwave Assoc.


Karthaus U.,Ubidyne GmbH | Sukumaran D.,Ubidyne GmbH | Tontisirin S.,Ubidyne GmbH | Ahles S.,Ubidyne GmbH | And 3 more authors.
IEEE Microwave and Wireless Components Letters | Year: 2012

A power amplifier, designed and fabricated in a low voltage GaAs hetero-junction bipolar transistor technology with a Doherty output stage, is presented. A pre-driver, a driver, main and peaking amplifiers, bias circuits, a 90° power splitter, and the Doherty impedance transformer are integrated on a single chip. Measured key performance parameters include a P1dB compression point of at least 38.8 dBm over the US digital dividend band ranging from 728 to 768 MHz, and a PAE of 37% for a 5 MHz long term evolution downlink signal with 7.16 dB peak-to-average ratio. © 2006 IEEE.


Karthaus U.,Ubidyne GmbH | Ahles S.,Ubidyne GmbH | Elmaghraby A.,Friedrich - Alexander - University, Erlangen - Nuremberg | Wagner H.,Ubidyne GmbH
International Journal of Microwave and Wireless Technologies | Year: 2013

This paper presents a radio frequency (RF) continuous-time band-pass delta sigma modulator (CT BP DSM) receiver realized in a 180 nm SiGe BiCMOS technology. It also provides an introduction to active antenna systems (AAS) for cellular infrastructure base stations, which is the target application for this RF integrated circuit (IC). The internal quantizer and feedback digital to analog converter (DAC) resolution of the CT BP DSM is 2 bit. Without applying DAC linearization techniques such as trimming or dynamic element matching being utilized, measured performance parameters include an SNR and SNDR in 35 MHz bandwidth of 56.7 and 53.7 dB, respectively. IIP3 and noise figure are -6.6 dBm and 10 dB, respectively. No image reception is noticeable within a measurement dynamic range of 83 dB. When driven by single-carrier and three-carrier W-CDMA signals, adjacent channel leakage ratio (ACLR) is -62.6 and -52.1 dB, respectively, making the design also suitable as a modulator for a class-S power amplifier. © Cambridge University Press and the European Microwave Association, 2013.


Zou L.,Ubidyne GmbH | Karthaus U.,Ubidyne GmbH | Sukumaran D.,Ubidyne GmbH | Mehrtash N.,Ubidyne GmbH | Wagner H.,Ubidyne GmbH
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2014

This paper presents a 6th order, 700-1100 MHz, 3.6-Gb/s sampling continuous-time band-pass sigma-delta (CT BP ΣΔ) ADC realized in 65 nm CMOS technology. A high linearity transconductance-stage with Miller effect cancellation is proposed to provide above 30 dBm IIP3 over PVT corners. A 4-bit quantizer and non-return to zero (NRZ) feedback DACs are engaged in this design. The post-layout simulation shows a maximum 67.2 dB two-tone SFDR in 1-MHz bandwidth, IIP3 and noise figure are 4.3 dBm and 17.3 dB, respectively. © 2014 IEEE.

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