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Leuven, Belgium

Tang B.,Liverpool John Moores University | Zhang W.D.,Liverpool John Moores University | Degraeve R.,TU PT Division | Breuil L.,TU PT Division | And 7 more authors.
IEEE Transactions on Electron Devices | Year: 2014

High density of electron trapping in high- \kappa intergate dielectric (IGD) materials remains a major concern for planar memory cells with either poly-Si or hybrid floating gates (FGs). In this paper, for the first time, using the ultrafast I{-}V measurements, it is demonstrated that a significant portion of the P/E windows are actually contributed by electrons trapped initially in the high- \kappa IGD stacks during program/erase, and then discharged to FG or control gate during verification. More importantly, it is demonstrated, for the first time, that this fast charge transition can be suppressed using novel multilayer high- \kappa IGD structures, and the fast window instability can be eliminated. © 1963-2012 IEEE. Source

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