Tower Semiconductor Ltd.

Migdal Ha‘Emeq, Israel

Tower Semiconductor Ltd.

Migdal Ha‘Emeq, Israel

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Patent
Tower Semiconductor Ltd. | Date: 2015-12-03

Gas sensing using MTJ elements to capture/store gas concentration level data for readout at room temperature. In one embodiment, during reset the MTJ elements are heated above blocking temperatures of their storage layers while applying a first magnetic biasing force to set initial magnetic orientations. During gas sensing, reaction heat from a gas sensing element combines with control heat to raise each MTJ elements temperature from a work point temperature above its blocking temperature only when the target gas exceeds an associated concentration level, whereby a second magnetic biasing force causes the magnetic orientation to switch directions. During readout, read currents are measured to determine the MTJ elements final resistance states, which indicate their switched/non-switched states, and the resistance states are correlated with stored data to determine the measured gas concentration level. The MTJ elements are cooled after reset and gas sensing to facilitate accurate CDS readout data.


Patent
Tower Semiconductor Ltd. | Date: 2015-12-03

A CMOS gas sensor that uses MTJ elements to capture/store gas concentration level data at high temperatures for later readout at low temperatures. Each MTJ element includes a storage layer whose magnetic orientation is switchable between parallel and anti-parallel directions relative to a fixed reference when heated above the storage layers blocking temperature, whereby the MTJ element is switchable between low and high resistance states. During operation, reaction heat generated by a gas sensing element raises the MTJ elements temperature above the blocking temperature when ambient target gas exceeds a minimum concentration level, whereby an applied magnetic biasing force causes the storage layers magnetic orientation to switch relative to the fixed reference, whereby the MTJ element captures measured concentration level data for later readout. In one embodiment, multiple MTJ elements connected in a NAND-type string switch at different concentration levels to provide highly accurate quantitative measurement data.


Patent
Tower Semiconductor Ltd. | Date: 2016-01-21

A method for manufacturing a metal insulator metal (MIM) trench capacitor, the method may include forming a cavity in an Intermetal Dielectric stack, wherein a bottom of the cavity exposes a lower metal layer; wherein the Intermetal Dielectric stack comprises a top dielectric layer; depositing a first metal layer on a bottom of a cavity and on sidewalls of the cavity; depositing a sacrificial layer over the first metal layer; filling the cavity with a filling material; removing, by a planarization process, a portion of the sacrificial layer positioned above the top dielectric layer and a portion of the first metal layer positioned above the top dielectric layer to expose an upper portion of the sacrificial layer and an upper portion of the first metal layer; forming a recess by removing the upper portion of the sacrificial layer and the upper portion the first metal layer while using the filling material as a mask; removing the filling material by a first removal process that is selective to the sacrificial layer and to the first metal layer; removing the sacrificial layer by a second removal process that is less aggressive than the first removal process; fabricating an insulator layer on the first metal layer; and depositing a second metal layer on the insulator layer


A backside illuminated semiconductor image sensor that includes a Fabry-Perot resonator tuned to absorb near infrared (NIR) radiation; wherein the Fabry-Perot resonator comprises a front reflector, a back reflector and an active Silicon layer between the front reflector and the back reflector.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-25-2015 | Award Amount: 4.54M | Year: 2016

The interest for developing smart systems based on interconnected objects is growing fast (50 billion objects connected in 2020). The main components of Internet of Things (IoT) devices are autonomous battery-operated smart embedded systems comprising communication circuits, sensors, computing/processing devices and storage. The key requirements are ultra-low power, high processing capabilities, fast/dense storage, wireless communication, heterogeneous integration, and autonomy. The different functions are so far implemented in separate chips/technologies, which is a bottleneck in terms of costs and miniaturization. To tackle the key issues of monolithic heterogeneous integration, fast yet low power processing, high integration density, fast yet low power storage, the goal of the GREAT STREP project is to co-integrate multiple functions like sensors (Sensing), RF receivers (Communicating) and logic/memory (Processing/Storing) together within CMOS by adapting the STT-MTJs (Magnetic devices) to a single baseline technology. This lead to a unique STT-MTJ cell technology called Multifunctional Standardized (MTJ) Stack (MSS), paving the way to 2.5D self-integrated heterogeneous architectures . The major outputs of GREAT are the technology and the architecture platform for IoT SoCs which provides better integration of embedded & mobile communication systems and a significant decrease of their power consumption. Based on the STT unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way. The project final objectives are: fabrication of an advanced MSS technology test chip jointly with a system-level simulation and design of a representative M2M IoT platform integrating MSS. The consortium is composed of 9 EU partners led by CEA and of an Advisory Board comprising leaders in IP solutions, IoT, and mobile technologies.


Patent
Tower Semiconductor Ltd. and RedCat Devices Srl | Date: 2015-06-29

An electronic device is proposed. The electronic device comprises: at least one electronic component formed in a chip of semiconductor material; at least one radioisotope power source unit comprising a radioactive material. The at least one radioisotope power source unit is embedded in the chip of semiconductor material together with the at least one electronic component. Moreover, the at least one radioisotope power source unit is arranged for providing electric power to said at least one electronic component by absorbing particles emitted by said radioactive material comprised in the least one radioisotope power source unit.


Patent
Tower Semiconductor Ltd. | Date: 2015-03-04

According to an embodiment of the invention there may be provided a die that may include a first capacitor layer that comprises (a) a first capacitor conductive plate, and (b) a first capacitor layer dielectric material that partially surrounds the first capacitor conductive plate; a first conductor; an intermediate metal layer that comprises (a) an intermediate metal layer conductor that is made of Copper, and (b) an intermediate metal layer dielectric material that partially surrounds the intermediate metal layer conductor; wherein the first conductor is positioned between a substrate of the die and the intermediate metal layer; a redistribution layer that comprises (a) a redistribution layer conductor that is electrically coupled to an interface pad of the die, (b) a second capacitor conductive plate, and (c) a redistribution layer dielectric material that partially surrounds the redistribution layer conductor and the second capacitor conductive plate; wherein a certain portion of the intermediate metal layer dielectric material is positioned between the first and second capacitor conductive plates; wherein at least the certain portion of the intermediate metal layer dielectric material, the first capacitor conductive plate and the second capacitor conductive plate form a high voltage capacitor; and wherein the intermediate metal layer conductor is configured to supply power to a group of transistors of the die while the first conductor is configured to supply power only to a sub-group of the transistors of the die.


Patent
Tower Semiconductor Ltd. | Date: 2015-03-23

A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.


A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field bump oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistors polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard bump mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistors drift (channel) region. The hard bump mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are self-aligned to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistors drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.


A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field bump oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistors polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard bump mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistors drift (channel) region. The hard bump mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are self-aligned to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistors drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.

Loading Tower Semiconductor Ltd. collaborators
Loading Tower Semiconductor Ltd. collaborators