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Migdal Ha‘Emeq, Israel

A logic unit for security engines or content addressable memory including Magnetic Tunnel Junction (MTJ) elements connected in series to form a NAND-type string, where each MTJ element includes a storage layer and a sense layer having different anti-ferromagnetic materials respectively having higher and lower blocking temperatures. During write/program, the string is heated above the higher blocking temperature, and magnetic fields are used to store bit values of a confidential logical pattern in the storage layers. The string is then cooled to an intermediate temperature between the higher and lower blocking temperatures and the field lines turned off to store bit-bar (opposite) values in the sense layers. During a pre-compare operation, the MTJ elements are heated to the intermediate temperature, and an input logical pattern is stored in the sense layers. During a compare operation, with the field lines off, a read current is passed through the string and measured.

A match-in-place-type compare operation utilizes a string of Magnetic Tunnel Junction (MTJ) elements including storage layers and sense layers having different anti-ferromagnetic structures respectively having higher and lower blocking temperatures. Confidential data is written into the storage layers of the MTJ elements by heating the elements above the higher blocking temperature, and then orienting the storage and sense layers in first storage magnetization directions using field lines. The elements are then cooled to an intermediate temperature between the higher and lower blocking temperatures, and the field lines are turned off, setting the sense layers to preliminary storage magnetization directions opposite to the first directions. During a pre-compare phase, an input logic pattern is written into the sense layers by heating to the intermediate temperature. During a compare operation, with the field lines turned off, resistance of the MTJ string is detected by passing a read current through the string.

Hebrew University of Jerusalem and Tower Semiconductor Ltd. | Date: 2013-03-14

A photovoltaic device includes lateral P-I-N light-sensitive diodes disposed on a silicon island formed by a P epitaxial layer and surrounded by trenches that provide lateral isolation, where the island is separated from the substrate by a porous silicon region that is grown under the island and isolates the lower portions of the photovoltaic device from the highly doped substrate. The trenches extend through the P epitaxial material into the P+ substrate to facilitate self-limiting porous silicon formation at the bottom of the island, and also to suppress electron-hole recombination. A protective layer (e.g., SiN) is formed on the trench walls to further restrict porous silicon formation to the bottom of the island. Black silicon on the trench walls enhances light capture. The photovoltaic devices form low-cost embedded photovoltaic arrays on CMOS IC devices, or are separated to produce low-cost, HV solar arrays for solar energy sources, e.g. for solar concentrators.

A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having two different charge-to-voltage conversion capacitors that read a single photodiode charge during a two-phase readout operation. The first capacitor has a lower capacitance and therefore higher conversion gain (sensitivity), and the second capacitor has a higher capacitance and therefore lower conversion gain (sensitivity). The two-phase readout operation samples the photodiode charge twice, once using the high sensitivity capacitor and once using the low sensitivity capacitor. The high sensitivity readout phase provides detailed low light condition data but is saturated under brighter light conditions, and the low sensitivity readout phase provides weak data under low light conditions but provides high quality image data under brighter light conditions. The final HDR image is created by combining both high and low sensitivity images into a single image while giving each of them the correct weighted value.

Tower Semiconductor Ltd. | Date: 2014-03-05

A soft-start circuit for a switching regulator (e.g., a buck converter) in which the soft-start circuit supplies a DC ramp voltage to the switch regulators pre-driver such that the pulsed gate voltage supplied to power switch during the initial soft-start operating phase includes a series of pulses having amplitudes that respectively gradually change (e.g., sequentially increase from 0V to the system operating voltage), whereby the regulated output voltage passed from the power switch to the load is gradually increased at a rate that prevents voltage overshoot and inrush current. The DC ramp voltage is generated, for example, by a current source that begins charging a capacitor at the beginning of the initial soft-start operating phase. This arrangement allows a constant-frequency ramp signal generated by a single oscillator to be shared by multiple switch regulators that are fabricated on an IC chip.

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