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Kawasaki, Japan

Tanabe N.,Toshiba R and nter | Hakozaki H.,Yokohama National University | Ando H.,Yokohama National University | Dohi Y.,Yokohama National University | And 2 more authors.
Journal of Supercomputing | Year: 2010

The performance of memory and I/O systems is insufficient to catch up with that of COTS (Commercial Off-The-Shelf) CPU. PC clusters using COTS CPU have been employed for HPC. A cache-based processor is far less effective than a vector processor in applications with low spatial locality. Moreover, for HPC, Google-like server farms and database processing, insufficient capacity of main memory poses a serious problem. Power consumption of a Google-like server farm or a high-end HPC PC cluster is huge. In order to overcome these problems, we propose a concept of a memory and network enhancer equipped with scatter and gather vector access functions, high-performance network connectivity, and capacity extensibility. Communication mechanisms named LHS and LHC are also proposed. LHS and LHC are architectures for reducing latency for mixed messages with small controlling data and large data body. Examples of the killer applications of this new type of hardware are presented. This paper presents not only concepts and simulations but also real hardware prototypes named DIMMnet-2 and DIMMnet-3. This paper presents the evaluations concerning memory issues and network issues. We evaluate the module with NAS CG benchmark class C and Wisconsin benchmarks as applications with memory issues. Although evaluation for CG class C is difficult with conventional cycle-accurate simulation methods, we obtained the result for class C with our original method. As a result, we find that the module can improve its maximum performance about 25 times more with Wisconsin benchmarks. However, the results on a cache-based PC show the cache-line flushing degrades acceleration ratio. This shows the high potential of the proposed extended memory module and processors in combination with DMA-based main memory access such as SPU on Cell/B.E. that does not need cache-line flushing. The LHS and LHC communication mechanisms are evaluated in this paper. The evaluations of their effects on latency are shown. © 2009 Springer Science+Business Media, LLC. Source

Kiahi K.,Toshiba R and nter | Kurata M.,Toshiba R and nter | Jmai K.,Toshiba Corporation | Seki N.,Toshiba Corporation
PESC Record - IEEE Annual Power Electronics Specialists Conference | Year: 2015

Three types of high power GTO's with voltage ratings of 600 to 1300V, and maximum gate turn-off currents of 200 to 600A were developed. Design considerations for realizing these devices will be described. In addition, various results will be demonstrated relating to the development of a VVVF inverter using these devices. © 1977 IEEE. Source

Hatakoshi G.-I.,Toshiba R and nter | Nunoue S.,Toshiba R and nter
Applied Physics Express | Year: 2012

Explicit expression for the Auger coefficient equation has been derived for wurtzite semiconductors. Calculated results for wurtzite InGaN indicated that the existence of a higher conduction band has a significant effect on the Auger recombination near the 450nm wavelength range. © 2012 The Japan Society of Applied Physics. Source

Tamura K.,Japan National Institute of Advanced Industrial Science and Technology | Tamura K.,ROHM Semiconductor | Kudou C.,Japan National Institute of Advanced Industrial Science and Technology | Kudou C.,Panasonic | And 4 more authors.
Materials Science Forum | Year: 2014

Epitaxial layer surfaces on 2° off-cut 4H-SiC Si-face substrates are more prone to generate step-bunching than on 4° off-cut substrates, which are observed by confocal microscopy with differential interference contrast. Two 76.2-mm wafers are situated adjacent to each other on a wafer holder with a 340-mm diameter in the CVD reactor to approximate growth on a 150-mm wafer. Triangular defect density of epitaxial layers on 2° off-cut substrates is found as low as 0.7 cm -2 within two 76.2-mm wafers. We also report distribution of 2° off-cut epitaxial layers within two 76.2-mm wafers: σ/mean = 3.3% for thickness and σ/mean = 7.3% for carrier concentration. © (2014) Trans Tech Publications, Switzerland. Source

Moritsuka F.,Toshiba R and nter | Okuni H.,Toshiba R and nter | Umeda T.,Toshiba R and nter
IEICE Transactions on Electronics | Year: 2011

We propose two types of active directional couplers to assure high TX cancellation: an asymmetric type and a symmetric type. For attaining low receiving through loss, coupling capacitors used in conventional couplers are replaced by amplifiers in the proposed active directional couplers. The asymmetric active directional coupler is composed of a small number of components and simple structure. The symmetric active directional coupler has wide-bandwidth TX cancellation. Measurement results show that receiving through loss of -5.3 dB and the TX cancellation of -67.6 dB are obtained in the asymmetric active directional coupler, and receiving through loss of -6.7 dB and the TX cancellation of -66.4 dB are obtained in the symmetric active directional coupler. Compared to the asymmetric active directional coupler, the symmetric active directional coupler has advantage of wider bandwidth of 1.25 MHz to reduce TX leakage of less than -55 dB. Both the proposed active directional couplers achieve high TX cancellation, and the symmetric active directional coupler can be applied in a UHF RFID system with 10-m communication range. Copyright © 2011 The Institute of Electronics, Information and Communication Engineers. Source

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