Tokyo, Japan
Tokyo, Japan

Tokyo Electron Limited , or TEL, is a Japanese electronics and semiconductor company headquartered in Akasaka, Minato-ku, Tokyo, Japan.TEL is best known as a supplier of equipment to fabricate integrated circuits , flat panel displays , and photovoltaic cells . Tokyo Electron Device , or TED, is a subsidiary of TEL specializing in semiconductor devices, electronic components, and networking devices.As of 2011, TEL is the largest manufacturer of IC and FPD production equipment in Japan and the third largest in the world. The company was founded as Tokyo Electron Laboratories, Inc. in 1963.On September 24, 2013 Tokyo Electron and Applied Materials announced a merger. If approved by government regulators, the combined company, to be called Eteris, would be the world's largest supplier of semiconductor processing equipment, with a total market value of approximately $29 billion. Wikipedia.


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Patent
Tokyo Electron | Date: 2017-01-24

A time for doping an electrode material on an electrode sheet with a lithium ion can be reduced. The electrode manufacturing apparatus includes a processing chamber 200 to and from which the electrode sheet is loaded and unloaded; and a lithium thermal spraying unit 210 configured to dope a carbon material C with the lithium ion by forming a lithium thin film on the carbon material of the electrode sheet W loaded into the processing chamber while melting and spraying lithium-containing powder. Further, the lithium thermal spraying unit 210 includes a lithium-containing powder supply unit 250 configured to discharge the lithium-containing powder toward the electrode material of the electrode sheet, and at least one heating gas supply unit 260 configured to supply a heating gas that melts the lithium-containing powder discharged from the lithium-containing powder supply unit.


A substrate processing system includes a film-forming device to form photosensitive film on substrate, an exposure device to expose the film on the substrate, a relay device to transfer the substrate between the film-forming and exposure devices, a warping data acquisition device to acquire measured warping data of the substrate, a communication device to perform data communication with the exposure device, and a control device including film-forming, relay, measuring, and communication control sub-devices. The film-forming sub-device controls the film-forming device to form the film on the substrate, the relay sub-device controls the relay device to transfer the substrate to the exposure device, the measuring sub-device controls the warping data acquisition device to acquire the data after the controlling by the film-forming sub-device prior to the controlling by the relay sub-device, and the communication sub-device controls the communication device to transmit the data to the exposure device.


Patent
Tokyo Electron | Date: 2016-11-09

A method of plasma etching includes an etching process that generates plasma from a process gas that includes fluorocarbon by using first high frequency power output by a first high frequency power source, and by the generated plasma, etches a low-k film with a metal-containing film as a mask. In the etching process, the first high frequency power is intermittently applied.


Techniques disclosed herein provide a method and fabrication structure for pitch reduction for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A hardmask is positioned first on an underlying layer or layers to be etched. A pattern of alternating materials is formed on the hardmask. One or more of the alternating materials can be preferentially removed relative to other materials to uncover a portion of the hardmask layer. The hardmask and the remaining lines of alternating material together form a combined etch mask defining sub-resolution features.


Patent
Tokyo Electron | Date: 2016-11-23

There is provided a method of measuring a temperature of a gas in a line connected to a gas supply source and a decompressor, the line being divided by a first, a second and a third valve into a first line between the first valve and the second valve and a second line between the second valve and the third valve. A first pressure rise rate of a gas in the first line is measured when introducing a gas at a predetermined flow rate into the first and the second line. A second pressure rise rate of a gas in the first line is measured when introducing a gas at a predetermined flow rate only into the first line. A gas temperature in the first line is calculated based on known inner volume of the second line, the first pressure rise rate, and the second pressure rise rate.


A semiconductor device containing a metal-insulator-semiconductor (MIS) contact and method of forming are described. The method includes providing a semiconductor substrate containing a contact region, depositing an insulator film on the contact region, the insulator film including a mixed oxide material containing TiO_(2 )and at least one additional metal oxide. The method further includes depositing a metal-containing electrode layer abutting the insulator film to form a MIS structure, and heat-treating the MIS structure to scavenge oxygen from the TiO_(2 )to the metal-containing electrode layer to form a MIS contact with oxygen vacancies in the TiO_(2). According to one embodiment the at least one additional metal oxide is selected from HfO_(2), ZrO_(2), Al_(2)O_(3), and combinations thereof, and the metal-containing electrode layer is selected from the group consisting of Ti metal, Al metal, Hf metal, Zr metal, Ta metal, Nb metal, and a combination thereof.


Patent
Tokyo Electron | Date: 2017-02-13

A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).


Patent
Tokyo Electron | Date: 2017-02-09

A substrate transfer chamber for unloading the substrates from the containers includes a housing-shaped main body and a plurality of container connecting mechanisms to which the containers are connected. In the main body, some of the container connecting mechanisms are arranged on top of one another in a height direction of the main body.


Patent
Tokyo Electron | Date: 2017-05-03

A method for anisotropically etching a feature in a Cu-containing layer includes providing a substrate having a Cu-containing layer and a patterned etch mask formed on the Cu-containing layer such that on exposed Cu-containing layer is exposed to processing through the patterned etch mask, passivating a first surface of the exposed Cu-containing layer, and inhibiting passivation of a second surface of the Cu-containing layer. A Cu compound is formed on said second surface of the Cu-containing layer, and the Cu compound is removed from the second surface of the Cu-containing layer to anisotropically etch a feature in the Cu-containing layer.


A method and apparatus for dry etching pure Cu and Cu-containing layers for manufacturing integrated circuits. The invention uses a directional beam of O-atoms with high kinetic energy to oxidize the Cu and Cu-containing layers, and organic compound etching reagents that react with the oxidized Cu to form volatile Cu-containing etch products. The invention allows for low-temperature, anisotropic etching of pure Cu and Cu-containing layers in accordance with a patterned hard mask or photoresist.

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