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Hamdioui S.,Technical University of Delft | Gizopoulos D.,National and Kapodistrian University of Athens | Guido G.,IMEC | Guido G.,Catholic University of Leuven | And 3 more authors.
Proceedings -Design, Automation and Test in Europe, DATE | Year: 2013

Forthcoming technology nodes are posing major challenges on the manufacturing of reliable (real-time) systems: process variations, accelerated degradation aging, as well as external and internal noise are key examples. This paper focuses on real-time systems reliability and analyzes the state-of-the-art and the emerging reliability bottlenecks from three different perspectives: technology, circuit/IP and full system. © 2013 EDAA.

Cherkaoui A.,Hubert Curien Laboratory | Fischer V.,Hubert Curien Laboratory | Aubert A.,Hubert Curien Laboratory | Fesquet L.,TIMA Laboratory
Proceedings - International Symposium on Asynchronous Circuits and Systems | Year: 2013

Self-timed rings are oscillators in which several events can evolve evenly-spaced in time thanks to analog effects inherent to the ring stage structure. One of their interesting features is that they provide precise high-speed multiphase signals. This paper presents a true random number generator that exploits the jitter of events propagating in a self-timed ring with a high entropy. Designs implemented in Alter a Cyclone III and Xilinx Virtex 5 devices provide high quality random bit sequences passing FIPS 140-1 and NIST SP 800-22 statistical tests at a high bit rate. © 2013 IEEE.

Cherkaoui A.,Hubert Curien Laboratory | Fischer V.,Hubert Curien Laboratory | Aubert A.,Hubert Curien Laboratory | Fesquet L.,TIMA Laboratory
Proceedings -Design, Automation and Test in Europe, DATE | Year: 2012

Many True Random Numbers Generators (TRNG) use jittery clocks generated in ring oscillators as a source of entropy. This is especially the case in Field Programmable Gate Arrays (FPGA), where sources of randomness are very limited. Inverter Ring Oscillators (IRO) are relatively well characterized as entropy sources. However, it is known that they are very sensitive to working conditions. This fact makes them vulnerable to attacks. On the other hand, Self-Timed Rings (STR) are currently considered as a promising solution to generate robust clock signals. Although many studies deal with their temporal behavior and robustness in Application Specific Integrated Circuits (ASIC), equivalent study does not exist for FPGAs. Furthermore, these oscillators were not analyzed and characterized as entropy sources aimed at TRNG design. In this paper, we analyze STRs as entropy sources for TRNGs implemented in FPGAs. Next, we compare STRs and IROs when serving as sources of randomness. We show that STRs represent very interesting alternative to IROs: they are more robust to environmental fluctuations and they exhibit lower extra-device frequency variations. © 2012 EDAA.

Costenaro E.,IRoC Technologies | Alexandrescu D.,IRoC Technologies | Belhaddad K.,IRoC Technologies | Nicolaidis M.,TIMA Laboratory
Journal of Electronic Testing: Theory and Applications (JETTA) | Year: 2013

Single Event Transients are considerably more difficult to model, simulate and analyze than the closely-related Single Event Upsets. The work environment may cause a myriad of distinctive transient pulses in various cell types that are used in widely different configurations. We present practical methods to help characterizing the standard cell library using dedicated tools and results from radiation testing. Furthermore, we analyze the SET propagation in logic networks using a standard (reference) serial fault simulation approach and an accelerated fault simulation technique, taking in account both logic and temporal considerations. The accelerated method provides similar results as the reference approach while offering a considerable increase in the simulation speed. However, the simulation approach may not be feasible for large (multi-million cells) designs that could benefit from static analysis methods. We benchmark the results of a static, probabilistic approach against the reference and accelerated methods. Finally, we discuss the integration of the SET analysis in a complete Soft Error Rate analysis flow. © 2013 Springer Science+Business Media New York.

Shen H.,Eve Company | Hamayun M.-M.,TIMA Laboratory | Petrot F.,TIMA Laboratory
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | Year: 2012

Integration of multiple heterogeneous processors into a single system-on-a-chip is a clear trend in embedded devices. Designing and verifying these devices requires high-speed and easy-to-build simulation platforms. Among the software simulation approaches, native simulation is a good candidate since the embedded software is executed natively on the host machine, and no instruction set simulator development effort is necessary. However, existing native simulation approaches are such that the simulated software shares the memory space of the modeled hardware modules and the host operating system, making impractical the support of legacy code running on the target platform. To overcome this issue seldom mentioned in the literature, we propose the addition of a transparent address space translation layer to separate the target address space from the host simulator one. For this, we exploit the hardware-assisted virtualization technology now available on most general-purpose processors. Experiments show that this solution does not degrade the native simulation speed, while keeping the ability to accomplish software performance evaluation. © 2012 IEEE.

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