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Vivet P.,CEA Grenoble | Beigne E.,CEA Grenoble | Lebreton H.,CEA Grenoble | Zergainoh N.-E.,TIMA
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Year: 2011

With growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core DVFS is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real MIMO Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved. © 2011 Springer-Verlag Berlin Heidelberg.


Jean-Mistral C.,CEA Grenoble | Basrour S.,TIMA
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2010

Scavenging energy from human motion is a challenge to supply low consumption systems for sport or medical applications. A promising solution is to use electroactive polymers and especially dielectric polymers to scavenge mechanical energy during walk. In this paper, we present a tubular dielectric generator which is the first step toward an integration of these structures into textiles. For a 10cm length and under a strain of 100%, the structure is able to scavenge 1.5μJ for a poling voltage of 200V and up to 40μJ for a poling voltage of 1000V. A 30cm length structure is finally compared to our previous planar structure, and the power management module for those structures is discussed. © 2010 Copyright SPIE - The International Society for Optical Engineering.


Frank T.,STMicroelectronics | Moreau S.,CEA Grenoble | Chappaz C.,STMicroelectronics | Arnaud L.,CEA Grenoble | And 3 more authors.
Proceedings - Electronic Components and Technology Conference | Year: 2012

The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D integration is studied. Impact of the TSV section size on EM lifetime and consideration of increasing metal level thickness are reported. Void nucleates and grows right after TSV, in the adjacent metal level. The TSV section size at metal level interface is critical for high EM performance. Thickness increase of metal level is revealed to not directly increase EM robustness, since irregular void nucleation and growth impact expected performances. © 2012 IEEE.


Frank T.,STMicroelectronics | Moreau S.,CEA Grenoble | Chappaz C.,STMicroelectronics | Leduc P.,CEA Grenoble | And 6 more authors.
Microelectronics Reliability | Year: 2013

In this paper, reliability of Through Silicon via (TSV) interconnects is analyzed for two technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2 μm diameter and 15 μm of depth. Thermal cycling and electromigration stresses are performed on dedicated devices. Thermal cycling is revealed to induce only defects on non-mature processes. Electromigration induces voids in adjacent metal level, right at TSV interface. Moreover, the expected lifetime benefit by increasing line thickness does not occur due to increasing dispersion of voiding mechanism. Second part covers reliability of Cu TSV-middle technology, of 10 μm diameter and 80 μm depth, with thermal cycling, BEoL dielectric breakdown, and electromigration study. Thermal cycling is assessed on two designs: isolated and dense TSV patterns. Dielectric breakdown tests underline an impact of TSV on the reliability of metal level dielectrics right above TSV. Electromigration reveal similar degradation mechanism and kinetic as on TSV-last approach. © 2012 Elsevier Ltd. All rights reserved.


The U.S. Senate is finally replacing BlackBerry devices with iPhones or Samsung smartphones. The Canadian mobile phone maker has been facing stiff competition from rivals and lost a major chunk of its business to other handset makers. BlackBerry devices have the reputation of being one of the most secure mobile phones and were used by members of the U.S. Senate for many years. "If we can secure the device, it makes securing the software and the data management...that much more easier," said John Chen, the CEO of BlackBerry. "This is why all the governments in the major developed countries are using our devices. You can see the heads of state using our devices." However, BlackBerry's U.S. Senate era is coming to an end as Senate staff will reportedly no longer receive new BlackBerry phones, and Apple or Samsung smartphones may replace them. A previous report highlighted that BlackBerry will discontinue BlackBerry 10 running devices, which could be a reason for the U.S. Senate to look for alternatives. However, BlackBerry denies such claims and says it will continue support for existing devices. Meanwhile, reports suggest that the U.S. Senate may consider giving the Samsung Galaxy S6 or iPhone SE to its staff. Android and iOS devices also have a strong security system. Both the operating systems offer data encryption, which is an important aspect of keeping content secured on a device. Samsung Knox, an enterprise mobile security system, may play an important role in attracting U.S. Senate staff. Knox has multi-layered security to keep the content of a device safe from any hacking attempts. "Knox Workspace is secured from the boot up. Only the Knox-hardened Android platform protects your infrastructure with multi-level, hardware-to-application security via Trusted Boot and ARM TrustZone-based Integrity Measurement Architecture (TIMA) to keep your business intelligence and network safe from hacking, viruses, and unauthorized access," says Samsung. Although Samsung may have high security features in its devices, Android operating systems face a lot of attacks from hackers every day. Security firm Duo Labs reported that Samsung devices are one of the safest devices in the smartphone space, that is, if they get security updates quickly. Apple also claims that iOS is designed in a way that offers users secure usage at all times. "Worldwide governments have collaborated with Apple and developed guides designed to give instructions and recommendations for maintaining a more secure environment," says Apple. However, Apple is involved in a heated debate with the FBI over encryption of its iPhones, which may make it difficult for the company to strike a deal with the U.S. Senate. It remains to be seen which mobile phone maker is able to convince the U.S. Senate with its security features and procure a deal in the near term. © 2017 Tech Times, All rights reserved. Do not reproduce without permission.


Chaix F.,TIMA | Avresky D.,IRIANC | Zergainoh N.-E.,TIMA | Nicolaidis M.,TIMA
Proceedings - 2010 9th IEEE International Symposium on Network Computing and Applications, NCA 2010 | Year: 2010

Future applications will require processors with many cores communicating through a regular interconnection network. Meanwhile, as the Deep submicron technology foreshadows highly defective chips era, fault-tolerant designs become compulsory. In particular, the fault tolerance of a core interconnect is critical, and inevitably increases its complexity. In this paper, we present a novel adaptive routing algorithm that is able to route messages in the presence of any set of multiple nodes and links failures, as long as a path exists. Compared to the existing solutions, the proposed algorithm provides fault tolerance without using any routing table. It is scalable and can be applied to multicore chips with a 2D mesh core interconnect of any size. The algorithm is deadlock-free and avoids infinite looping in fault-free and faulty 2D meshes, based on Virtual Networks and Virtual Channels. We simulated the proposed algorithm using the worst case scenario, regarding the traffic patterns and the failure rate up to 40%. Experimentation results confirmed that the algorithm tolerates multiple failures even in the most extreme failure patterns. Additionally, we monitored the trade off between the fault tolerance and the average latency for faulty cases, as measurement of the performance degradation. The algorithm detects the interconnects partitioning and enables "preferred paths" for streaming applications. © 2010 IEEE.


Chaix F.,TIMA | Avresky D.,IRIANC | Zergainoh N.-E.,TIMA | Nicolaidis M.,TIMA
Proceedings -Design, Automation and Test in Europe, DATE | Year: 2011

Future applications will require processors with many cores communicating through a regular interconnection network. Meanwhile, the Deep submicron technology foreshadows highly defective chips era. In this context, not only fault-tolerant designs become compulsory, but their performance under failures gains importance. In this paper, we present a deadlock-free fault-tolerant adaptive routing algorithm featuring Explicit Path Routing in order to limit the latency degradation under failures. This is particularly interesting for streaming applications, which transfer huge amount of data between the same source-destination pairs. The proposed routing algorithm is able to route messages in the presence of any set of multiple nodes and links failures, as long as a path exists, and does not use any routing table. It is scalable and can be applied to multicore chips with a 2D mesh core interconnect of any size. The algorithm is deadlock-free and avoids infinite looping in fault-free and faulty 2D meshes. We simulated the proposed algorithm using the worst case scenario, with different failure rates. Experimentation results confirmed that the algorithm tolerates multiple failures even in the most extreme failure patterns. Additionally, we monitored the interconnect traffic and average latency for faulty cases. For 20x20 meshes, the proposed algorithm reduces the average latency by up to 50%. © 2011 EDAA.


Sivadasan A.,STMicroelectronics | Cacho F.,STMicroelectronics | Benhassain S.A.,STMicroelectronics | Huard V.,STMicroelectronics | Anghel L.,TIMA
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 | Year: 2016

Workload characterization of digital circuits using industry standard benchmarks gives an insight into the performance and energy characteristics of processor designs. Aging studies of digital circuits due to BTI, HCI is gaining importance since a higher impact on the performance of circuits can be observed as we scale down gate dimensions. For embedded system applications, the workload may very well dictate the lifetime of a system. This article aims to study the influence of different workloads on the degradation of critical path which determines the reliability of a system. A top-down circuit activity and probability analysis is carried out leading to an accurate estimation of aging due to HCI and BTI of critical path elements at the design stage. A dedicated simulation flow has been set up, from RTL simulation down to gate level cell timing analysis mapped onto 28nm FDSOI technology from STMicroelectronics. The objective is to correlate path delay timing with aging of critical path cells. Simulation results indicate that the higher complexity of an execution program may not necessarily lead to a higher rate of degradation of the critical path considering that aging is primarily driven by the workload dependent activity and the probability of critical path combinational logic elements. © 2016 EDAA.


Benhassain A.,STMicroelectronics | Cacho F.,STMicroelectronics | Huard V.,STMicroelectronics | Anghel L.,TIMA
CEUR Workshop Proceedings | Year: 2016

In-situ monitor is a promising strategy to measure timing slacks and to provide pre-error warning prior to any timing violation. In this work, we demonstrate that the usage of in-situ monitors with a feedback loop of voltage regulation is suitable for process and temperature compensation. Copyright © 2016 for the individual papers by the papers' authors.


Charif A.,TIMA | Zergainoh N.-E.,TIMA | Nicolaidis M.,TIMA
Proceedings of the 21st IEEE International On-Line Testing Symposium, IOLTS 2015 | Year: 2015

NoCs (Networks-on-Chip) are an attractive alternative to communication buses for SoCs (Systems-on-Chip) as they offer both high scalability and low power consumption. However, designing such systems in the nanoscale era brings up some serious concerns about reliability. Our aim is to design robust NoCs while limiting performance degradation. In this paper, we introduce several techniques meant to increase the reliability and performance of NoCs. We combine these techniques to build a fault-tolerant, deadlock-free and congestion-aware routing algorithm called MUGEN. The algorithm comprises an optimized method to exchange messages between different virtual channel classes, a selection function that uses distant router link information to avoid dead-ends and a new congestion metric used to guide routing decisions towards less congested areas. We simulate an 8×8 Mesh NoC with fault injection to evaluate each method used by MUGEN individually before comparing the full algorithm with existing works from literature. We present promising results about the proposed techniques both in terms of fault-tolerance and performance. © 2015 IEEE.

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