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Grenoble, France

Vivet P.,CEA Grenoble | Beigne E.,CEA Grenoble | Lebreton H.,CEA Grenoble | Zergainoh N.-E.,TIMA
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

With growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core DVFS is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real MIMO Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved. © 2011 Springer-Verlag Berlin Heidelberg. Source

Jean-Mistral C.,CEA Grenoble | Basrour S.,TIMA
Proceedings of SPIE - The International Society for Optical Engineering

Scavenging energy from human motion is a challenge to supply low consumption systems for sport or medical applications. A promising solution is to use electroactive polymers and especially dielectric polymers to scavenge mechanical energy during walk. In this paper, we present a tubular dielectric generator which is the first step toward an integration of these structures into textiles. For a 10cm length and under a strain of 100%, the structure is able to scavenge 1.5μJ for a poling voltage of 200V and up to 40μJ for a poling voltage of 1000V. A 30cm length structure is finally compared to our previous planar structure, and the power management module for those structures is discussed. © 2010 Copyright SPIE - The International Society for Optical Engineering. Source

Frank T.,STMicroelectronics | Moreau S.,CEA Grenoble | Chappaz C.,STMicroelectronics | Arnaud L.,CEA Grenoble | And 3 more authors.
Proceedings - Electronic Components and Technology Conference

The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D integration is studied. Impact of the TSV section size on EM lifetime and consideration of increasing metal level thickness are reported. Void nucleates and grows right after TSV, in the adjacent metal level. The TSV section size at metal level interface is critical for high EM performance. Thickness increase of metal level is revealed to not directly increase EM robustness, since irregular void nucleation and growth impact expected performances. © 2012 IEEE. Source

Benhassain A.,STMicroelectronics | Cacho F.,STMicroelectronics | Huard V.,STMicroelectronics | Anghel L.,TIMA
CEUR Workshop Proceedings

In-situ monitor is a promising strategy to measure timing slacks and to provide pre-error warning prior to any timing violation. In this work, we demonstrate that the usage of in-situ monitors with a feedback loop of voltage regulation is suitable for process and temperature compensation. Copyright © 2016 for the individual papers by the papers' authors. Source

Frank T.,STMicroelectronics | Moreau S.,CEA Grenoble | Chappaz C.,STMicroelectronics | Leduc P.,CEA Grenoble | And 6 more authors.
Microelectronics Reliability

In this paper, reliability of Through Silicon via (TSV) interconnects is analyzed for two technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2 μm diameter and 15 μm of depth. Thermal cycling and electromigration stresses are performed on dedicated devices. Thermal cycling is revealed to induce only defects on non-mature processes. Electromigration induces voids in adjacent metal level, right at TSV interface. Moreover, the expected lifetime benefit by increasing line thickness does not occur due to increasing dispersion of voiding mechanism. Second part covers reliability of Cu TSV-middle technology, of 10 μm diameter and 80 μm depth, with thermal cycling, BEoL dielectric breakdown, and electromigration study. Thermal cycling is assessed on two designs: isolated and dense TSV patterns. Dielectric breakdown tests underline an impact of TSV on the reliability of metal level dielectrics right above TSV. Electromigration reveal similar degradation mechanism and kinetic as on TSV-last approach. © 2012 Elsevier Ltd. All rights reserved. Source

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