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You B.L.,HuanOu Semiconductor Material Technology Co. | Zhang X.N.,HuanOu Semiconductor Material Technology Co. | Luo C.,Tianjin ZhongHuan Advanced Material Technology Co. | Sun X.K.,Tianjin ZhongHuan Advanced Material Technology Co. | And 3 more authors.
Materials Science Forum | Year: 2015

With the development of power electronic devices, the market demand for acid etched wafers of monocrystalline silicon, which has good surface properties and minimum surface roughness, increases rapidly. But there has been rarely report about the impact of acid etching process on the wafer surface roughness. This paper studied the surface roughness of the wafer, which was etched by mixture of HNO3, HF and HAC. The results showed that the surface roughness became smaller with the increase of wafer remove amount, while the roughness became worse with the service life extension of the acid; however, fluid infusion discharge method could be adopted in the etching process so that the etching acid system could achieve a relatively balanced state and wafer roughness became stabilized. The process mechanism was studied and analyzed in this investigation. © (2015) Trans Tech Publications, Switzerland. Source


Dou B.,CAS Institute of Microelectronics | Jia R.,CAS Institute of Microelectronics | Li H.,CAS Institute of Microelectronics | Chen C.,CAS Institute of Microelectronics | And 5 more authors.
Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics | Year: 2012

A two-step maskless method was used to synthesize silicon nanostructures. In the first step, silver nanoparticles were formed through rapid thermal annealing of silver thin films. The temperature, duration of annealing, and initial thickness of the silver film jointly determined the distribution and diameter of silver particles. In the next step, silicon nanostructures were created using silver catalyzed etching in HF/H2O2. The experiment confirmed that the final sizes of the nanostructures corresponded to the diameters of the silver particles. Further, silicon nanostructure-textured solar cells were manufactured and tested. The surface-reflection ratio of the cells can be decreased to 5% in the 300-1000 nm wavelength range. The current-voltage and quantum efficiency measurements also reveal that silicon nanostructure-textured solar cells exhibit considerable light trapping enhancement. The results also indicate that effective passivation and electrode contact are important for those cells. © 2012 American Vacuum Society. Source


Wang Y.F.,Tianjin Zhonghuan Semiconductor Co. | Wang Y.F.,Tianjin University | Chen H.Y.,Tianjin Zhonghuan Semiconductor Co. | Zhang B.,Tianjin Zhonghuan Semiconductor Co. | And 3 more authors.
Advanced Materials Research | Year: 2014

In this paper, failure analysis was conducted to investigate the root cause of Ti/Ni/Ag film peeling from silicon wafer surface. SEM and Edax analysis revealed that peeling was found at Ti/Si interface, and no contamination elements, such as C, H, O, were existed. VK Analyzer was used to measure the surface roughness, and the results revealed that the peeling failure was due to the low surface roughness resulted from excessive polishing after wafer back grinding process. Experiments for changing rabbling polishing method for bubbling polishing one were done expecting to realize high uniformity of surface roughness, and the results showed that roughness uniformity was greatly improved, and no peeling metal was left on the blue tape. © (2014) Trans Tech Publications, Switzerland. Source


Jiang H.,University of Electronic Science and Technology of China | Zhang B.,University of Electronic Science and Technology of China | Chen W.,University of Electronic Science and Technology of China | Qiao M.,University of Electronic Science and Technology of China | And 4 more authors.
Electronics Letters | Year: 2012

A low turnoff loss snapback-free reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with a novel collector structure is demonstrated. The n-collector is partially enclosed by a floating p-layer (p-float) which acts as a barrier for electrons at low current in the forward conduction state and contributes to the snapback-free forward conduction characteristics. The p-float makes the proposed device feature double n-p-n electron extraction paths, the n-drift/p-float/n-collector (n-p-n1, n-drift is emitter) and the n-buffer/p-float/n-collector (n-p-n2, n-buffer is emitter), both of which can be activated during turnoff. As numerical simulations show, the two n-p-n extraction paths, especially n-p-n2 which is more effective than n-p-n1, are favourable to the ultra-low turnoff loss. © 2012 The Institution of Engineering and Technology. Source


Jiang H.,University of Electronic Science and Technology of China | Zhang B.,University of Electronic Science and Technology of China | Chen W.,University of Electronic Science and Technology of China | Li Z.,University of Electronic Science and Technology of China | And 4 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2012

A simple method to design the single-mask multi-zone junction termination extension (MZJTE) (SM-MZJTE) for high-voltage insulated-gate bipolar transistor (IGBT) is presented and experimentally demonstrated. By assuming that the p-type SM-MZJTE region is completely depleted and the equipotential lines are circular arcs for simplicity, an analytical model of the selective function is derived from the charge balance and the geometrical relations. As the blocking capability is sensitive to the implantation dose, the Boron segregation at Si-SiO 2 interface has also been taken into consideration in this model. According to the analytical model, high-voltage IGBTs and test devices with edge termination of SM-MZJTE are fabricated. IGBTs with edge termination implantation dose of 3×10 12 cm -2 show highest average breakdown voltage of 3.79 kV (about 92% of the parallel plane breakdown voltage). © 2012 IEEE. Source

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