Dallas, TX, United States
Dallas, TX, United States

Texas Instruments Inc. is an American electronics company that designs and makes semiconductors, which it sells to electronics designers and manufacturers globally. Headquartered at Dallas, Texas, United States, TI is the third largest manufacturer of semiconductors worldwide after Intel and Samsung, the second largest supplier of chips for cellular handsets after Qualcomm, and the largest producer of digital signal processors and analog semiconductors, among a wide range of other semiconductor products, including calculators, microcontrollers and multi-core processors. Texas Instruments is among the Top 20 Semiconductor producing companies in the world.Texas Instruments was founded in 1951. It emerged after a reorganization of Geophysical Service. This company manufactured equipment for use in the seismic industry as well as defense electronics. TI began research in transistors in the early 1950s and produced the world's first commercial silicon transistor. In 1954, Texas Instruments designed and manufactured the first transistor radio and Jack Kilby invented the integrated circuit in 1958 while working at TI's Central Research Labs. The company produced the first integrated circuit-based computer for the U.S. Air Force in 1961. TI researched infrared technology in the late 1950s and later made radar systems as well as guidance and control systems for both missiles and bombs. The hand-held calculator was introduced to the world by TI in 1967.In the 1970s and 80s the company focused on consumer electronics including digital clocks, watches, hand-held calculators, home computers as well as various sensors. In 1997, its defense business was sold to Raytheon. In 2007, Texas Instruments was awarded the Manufacturer of the Year for Global Supply Chain Excellence by World Trade magazine. Texas Instruments is considered to be one of the most ethical companies in the world.After the acquisition of National Semiconductor in 2011, the company has a combined portfolio of nearly 45,000 analog products and customer design tools, making it the world's largest maker of analog technology components. In 2011, Texas Instruments ranked 175 in the Fortune 500. TI is made up of two main divisions: Semiconductors and Educational Technology of which Semiconductor products account for approximately 96% of TI's revenue. Wikipedia.


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Patent
Texas Instruments | Date: 2017-03-15

Contacts are formed to integrated circuit devices by first forming a conductive layer (80) on a semiconductor device. An optional dielectric layer (130) is formed over the conductive layer and a carbon containing dielectric layer (140) is formed over the optional dielectric layer (130). Contacts are formed to the conductive layer (80) by etching openings in the carbon containing dielectric layer (140) and the optional dielectric layer (130).


Patent
Texas Instruments | Date: 2017-02-22

A serial bus network includes a voltage regulator, a plurality of power switches, and a voltage monitor. The voltage regulator provides power to a plurality of serial buses. Each of the serial buses provides power from the voltage regulator to a device coupled to the serial bus. Each of the power switches power from the voltage regulator to one of the serial buses, and includes an input terminal coupled to a voltage regulator output, and an output terminal coupled to one of the serial buses. The voltage monitor is coupled to the voltage regulator and to the output terminal of each of the power switches. The voltage monitor compares bus voltages at the output terminals of the power switches, identifies a lowest of the bus voltages, and adjusts the voltage regulator output voltage such that the identified lowest of the bus voltages is within a predetermined operational voltage range.


Grant
Agency: European Commission | Branch: H2020 | Program: CSA | Phase: ICT-25-2015 | Award Amount: 1.16M | Year: 2016

Understanding properties of nanoparticles (and in general of nano-functionalized materials) and how they behave in living systems is a relatively new area of scientific study. The scientific community has not yet been able to derive harmful properties of nanomaterials from the properties of the bulk material. So a precautionary approach is required when handling and using these materials in circumstances where exposure to nanomaterials cannot be excluded. The purpose of this project is to promote good practices (i.e. by following up standards), identify gaps in methodologies and direction for further investigations in order to support risk assessment in order to protect human health. The project also aims to initiate communication with stakeholders to support informed decision making and governance of risks related to handling of nanomaterials and medical surveillance of the workforce in the semiconductor fabrication process. We will focus on several use cases. For example, the use of nanomaterials in chemical mechanical polish slurries for semiconductor manufacture is well documented; however there are also other scenarios where nanomaterials may be used or generated (e.g. wafer cleaving, cleaning of rector chambers or exhaust air ducts).


Patent
Texas Instruments | Date: 2016-09-08

The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.


Patent
Texas Instruments | Date: 2016-08-23

A memory interleaver includes a channel selection unit to receive a system memory address for a memory request. The interleaver also includes a local memory address computation unit and a de-multiplexer. The channel selection unit examines a predetermined plurality (n) of bits in a memory address of a memory transaction and assigns the memory transaction to one of a plurality of memory channels in a multi-channel memory unit based on a state of the predetermined plurality of bits. Preferably, 2^(n )is greater than the number of memory channels in the multi-channel memory unit.


This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.


In described examples of an illumination system, the illumination system includes: at least two illumination modules to output different color light beams to an illumination path; and illumination optics corresponding to each of the at least two illumination modules to receive the light beams and to provide illumination to a programmable spatial light modulator. The programmable spatial light modulator receives the illumination and outputs patterned light to projection optics. The projection optics receive the patterned light and output the patterned light as an output beam through a lens. A controller controls the intensity and duration of light output from the at least two illumination modules and controls the pattern of the spatial light modulator. The output beam is a color formed by combining the different color light beams. The output beam is spectrally tunable.


An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.


Patent
Texas Instruments | Date: 2016-08-22

An integrated circuit includes combinational logic with flip-flops, parallel scan paths with a scan input for receiving test stimulus data to be applied to the combinational logic, combinational connections with the combinational logic for applying stimulus data to the combinational logic and receiving response data from the combinational logic, a scan output for transmitting test response data obtained from the combinational logic, and control inputs having an enable input and a select input for operating the parallel scan paths, each scan path includes flip-flops of the combinational logic that, in a test mode, are connected in series, compare circuitry indicates the result of a comparison of the received test response data and the expected data at a fail flag output, and one of the scan paths includes a scan cell having an input coupled to the fail flag output.


Patent
Texas Instruments | Date: 2016-04-27

An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

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