United States
United States

Teradyne , based in North Reading, Massachusetts in the United States, is a developer and supplier of automatic test equipment . The company's divisions Semiconductor Test and Systems Test Group, are organized by the products they develop and deliver. Teradyne's high-profile customers include Samsung, Qualcomm, Intel, Analog Devices, Texas Instruments and IBM. Wikipedia.


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Patent
Teradyne Inc. | Date: 2015-08-05

Apparatus and methods for calibrating tester channels of an automated test system are described. A relay matrix assembly comprising a plurality of microelectromechanical (MEM) switches may be used to connect a plurality of tester channels to analyzer calibration instrument rapidly without requiring serial, robotic probing of the test channels. The relay matrix assembly may be constructed on a printed circuit board that can be attached to an interface on the tester. Calibration parameters for the test channels may be calculated from waveforms received through the relay matrix assembly and that have been corrected to remove waveform distortion introduced by the relay matrix assembly. Parameters to correct for distortion in the relay matrix assembly may be measured in advance and stored for use when calibration is to be performed.


Patent
Teradyne Inc. | Date: 2015-08-31

A test system includes a transporter having test sockets, where each test socket is configured to receive a device to be tested by the test system, and each test socket includes an element that is controllable to change a temperature of a device in the test socket through thermal conduction. The test system includes a test rack comprising slots. The transporter is configured for movement into, and out of, a slot of the test rack to test devices in the test sockets.


Patent
Teradyne Inc. | Date: 2014-08-21

A probe for automatic test equipment (ATE) includes: an outer shroud including a course alignment feature configured to receive a target device and to guide the target device into an interior of the outer shroud, where the target device includes exposed electrical leads; and an inner structure that is at least partly inside the outer shroud. The inner structure includes electrical contacts for making an electrical connection to the exposed electrical leads, and also includes a fine alignment feature configured to guide the target device towards the electrical contacts to make the electrical connection.


Patent
Teradyne Inc. | Date: 2014-08-25

A probe assembly for capacitive testing electrical connections of a low profile component to a circuit assembly. The probe assembly is configured to reduce coupling of noise signals from the circuit assembly to the capacitive probe. The probe assembly includes a sensing member with a geometry that allows the probe to preferentially couple to test signals from the pins of a component under test rather than conductive structures on the circuit assembly, such as pads, and signal traces to which those pins are attached. The sensing member may be a vertical capacitive sense plate such that coupling is to an edge of the plate. The sensing member alternatively may be a horizontal capacitive sense plate with an active area of the probe surrounded by an isolation ring. Measurements made with such capacitive probes may provide test measurements that yield a reliable discrimination between a properly attached pin and an open pin.


Patent
Teradyne Inc. | Date: 2015-09-24

An example gripper may include: a base; two or more fingers attached to the base, with each finger being movable towards, and away from, one or more others of the fingers; and one or more ports at the base or at one or more of the fingers to provide suction through a vacuum.


A test system and test techniques for accurate high current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.


A test system and test techniques for accurate high-current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.


Patent
Teradyne Inc. | Date: 2015-02-19

A testing device for testing a radar device. The testing device may be configured to determine a first frequency difference between a frequency of a first signal or a second signal and a frequency of a third signal based on a first distance value; transmit to the radar device the first signal; receive the second signal from the radar device; transmit to the radar device the third signal at an offset relative to at least one of the first signal and the second signal based on the first frequency difference; and receive from the radar device a fourth signal indicating a second distance value or a second frequency difference between the frequency of the second signal and the frequency of the third signal, determined by the radar device, for comparison with the first distance value or the first frequency difference.


An electronic system, comprising a first semiconductor device, a second semiconductor device, a clock circuit, and a plurality of independently adjustable calibration circuits connected in each of the plurality of serial data paths. The first semiconductor device may comprise a plurality of Serializer-Deserializer interfaces. The second semiconductor device may comprise a plurality of serial data interfaces coupled to the plurality of Serializer-Deserializer interfaces to provide a plurality of serial data paths between the first semiconductor device and the second semiconductor device. The plurality of Serializer-Deserializer interfaces and the plurality of serial data interfaces may be clocked from a clock signal derived from the clock circuit. The plurality of independently adjustable calibration circuits may be configured to compensate for timing differences across the plurality of serial data paths.


Patent
Teradyne Inc. | Date: 2015-04-16

An example test system includes a bus interface to connect to a bus of a computer system; and test instruments to perform one or more test operations on a UUT, where the test instruments connect to the bus interface to enable communication between the computer system and the test instruments via the bus interface. At least one test instrument includes: ports to which the UUT is connectable, with each of the ports interfacing to a corresponding peripheral bus supported by the at least one test instrument; circuits to connect the bus interface to the peripheral buses, with each circuit being configured to convert between a bus interface protocol run on the bus interface and a peripheral bus protocol run on a peripheral bus; and a switch to identify a target circuit of the circuits, with the switch to direct communications between the computer system and the target circuit.

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