Tsai M.-Y.,Chang Gung University |
Huang P.-S.,Chang Gung University |
Huang C.-Y.,Chang Gung University |
Jao H.,Technology Development Division |
And 8 more authors.
IEEE Transactions on Electron Devices | Year: 2013
The technology of through silicon via (TSV) is one of the most promising enablers for 3-D integrated circuit (IC) integration. The embedded TSVs in silicon chips would, however, cause the problem of carrier mobility changes in surrounding devices. There are two objectives in this paper. The first objective is to numerically and experimentally investigate the effect of via-middle Cu TSV on the mobility change of metal-oxide-semiconductor transistors in the wafer-level silicon chips for this 3-D IC integration. The second objective is to further determine the keep-out zone (KOZ) in terms of the key parameters such as the SiO2 layer effect, the zero-stress temperature, the single and array vias, the through and blind vias, silicon material properties, as well as the diameter and pitch of vias. KOZs based on the >10\% change in carrier mobility are identified by finite element numerical calculations associated with the corresponding piezoresistance coefficients. The numerical results of the changes in saturated current are experimentally validated with good agreements. With the results of detailed analyzes using this validated model, the key parameters affecting the KOZs are presented and further discussed in detail. © 1963-2012 IEEE. Source