Time filter

Source Type

Keelung, Taiwan

Lu F.C.,Chang Gung University | Keng H.T.,Chang Gung University | Liu H.Y.,Chang Gung University | Tsai M.Y.,Chang Gung University | Lin P.C.,Technology Development Div
2016 International Conference on Electronics Packaging, ICEP 2016 | Year: 2016

The purpose of this study is to evaluate the strength of TSV silicon chips using a point-load on elastic foundation (PoEF) test, associated with an acoustic emission (AE) method for detecting local material cracks or delamination occurring during the test before the chip breaking (or catastrophic failure). The results indicate that there are no larger-than-25 dB AE signals and no via cracks occurring before the chip breaking. However, the delamination between copper cap and silicon dioxide surface (due to poor adhesion), and bond pad crash on loading contact were found occurring with 50 dB of AE signals, respectively. It has been concluded that the strength of TSV chip is governed by the via interfacial crack failure occurring right at the maximum load. © 2016 The Japan Institute of Electronics Packaging. Source

Tsai M.Y.,Chang Gung University | Huang P.S.,Chang Gung University | Huang C.Y.,Chang Gung University | Lin P.C.,Technology Development Div | And 4 more authors.
Microelectronics Reliability | Year: 2014

This paper aims to measure and simulate the warpages of 3D through-silicon via (TSV) die-stacked dynamic-random-access-memory (DRAM) packages during the manufacturing process. The related die stresses and keep-out zone (KOZ) for the stacked dies in the packages at room temperature are further calculated with the validated simulation model. The out-of-plane deformations (or warpages) of the packages from the full-field shadow moiré are documented under temperature loading and found consistent with those from finite-element method (FEM). The results of the stresses and KOZs at the proximity of a single TSV for each die in the package at room temperature are presented. It is found that the sizes of KOZs in four-die stacked DRAM packages with and without epoxy molding compound (EMC) at room temperature are dominated by the horizontal pMOS transistors and more than double the size in wafer-level die. The sizes of KOZs at each die are similar in this four-die stacked DRAM package, even though the stresses at each die are apparently different. © 2014 Elsevier Ltd. All right reserved. Source

Discover hidden collaborations