Technology Center America

Albany, NY, United States

Technology Center America

Albany, NY, United States
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Bhuyian M.N.,New Jersey Institute of Technology | Sengupta A.,Heritage Institute of Technology | Ding Y.,New Jersey Institute of Technology | Misra D.,New Jersey Institute of Technology | And 5 more authors.
ECS Transactions | Year: 2017

In this work, we have investigated the impact of Slot-Plane Antenna Plasma Oxidation (SPAO) on TiN/Hf1-xZrxO2/Al2O3/Ge gate stack with six different Zr content (0%, 25%, 33%, 50%, 75%, and 100%) in the dielectrics. The dielectrics were subjected to SPAO after the ALD deposition process prior to metal deposition. The equivalent oxide thickness (EOT), flat-band voltage (VFB), interface state density (Dit), C-V hysteresis, and leakage current (I-V) behavior were analyzed. It was observed that EOT decreases with Zr addition in HfO2 with up to 75% of Zr incorporation. While the devices with up to 75% of Zr demonstrated lower C-V hysteresis, flat-band voltage shift and mid-gap Dit tend to increase with decrease in EOT. With 100% Zr incorporation EOT increased significantly while reducing the mid-gap Dit. This behavior is mostly dependent on GeOx-like interfacial layer formation and defects at the interface. © The Electrochemical Society.

Ang K.-W.,SEMATECH | Majumdar K.,SEMATECH | Matthews K.,SEMATECH | Young C.D.,SEMATECH | And 11 more authors.
Technical Digest - International Electron Devices Meeting, IEDM | Year: 2012

We demonstrate statistically significant data for specific contact resistivity (ρc) of sub-10-8Ω-cm2 and sub-2×10-8Ω-cm2 for N-type and P-type Si respectively on 300mm wafer by introducing ultra-thin ALD high-k dielectric layer(s) between the metal and Si. A 6-terminal Cross-Bridge Kelvin (6T-CBK) structure was used for the extraction to achieve excellent resolution in this small ρc range. With the help of measurements from multiple dielectric stacks and Non-Equilibrium Green's Function (NEGF) based quantum transport calculations, we clearly show that the suppression of evanescent metal induced gap states (MIGS) and formation of interface dipole play significant role to reduce the ρc as long as the tunneling resistance of the dielectric stack is small. Finally, transient response, break down mechanism and technology benchmarking are discussed which show promise for sub-14nm node applications. © 2012 IEEE.

Vartanian V.,SEMATECH | Hummler K.,Trethorne Dr. | Olson S.,University at Albany | Barbera T.,TEL NEXX Inc. | And 11 more authors.
Proceedings - 2014 47th International Symposium on Microelectronics, IMAPS 2014 | Year: 2014

Even as unit processes for high aspect ratio (HAR) through silicon via (TSV) mid-wafer front-side processing are becoming relatively mature, scaling of the TSVs and reduction of cost of ownership (COO) drive significant innovations in processes, equipment and materials. To assess their high volume manufacturing (HVM) worthiness, any new unit processes need to be evaluated with respect to yield, reliability and COO. Fully integrated product runs tend to be too slow and expensive for this purpose. At SEMATECH, we use TSV mid-wafer short loop test vehicles for rapid learning cycles through in-line electrical test (ILT) and wafer-level reliability assessments using voltage ramp dielectric breakdown (VRDB). These test vehicles contain 5 × 50 μm or 2 × 40 μm TSV comb test structures, which are testable after the first front-side metal line layer level. Novel unit processes by our associate member companies are inserted into the process flow, and are optimized and assessed using split lot experiments. Processes including TSV etch, post TSV etch cleans, dielectric liner deposition, Cu diffusion barrier and seed deposition, as well as TSV fill by Cu electrochemical deposition (ECD) were evaluated. ILT and VRDB results for short loop lots are presented and discussed. Copyright ©2014 IMAPS-International Microelectronics Assembly and Packaging Society.All Rights Reserved.

Vartanian V.,SEMATECH | Smith L.,SEMATECH | Hummler K.,2 Trethorne Dr. | Olson S.,University at Albany | And 12 more authors.
Proceedings - 2014 47th International Symposium on Microelectronics, IMAPS 2014 | Year: 2014

SEMATECH evaluated the impact of various process options on the overall manufacturing cost of a TSV module, from TSV lithography and etch through post-plate CMP. The purpose of this work was to understand the cost differences of these options in order to identify opportunities to significantly reduce cost. Included in this study were multiple process and materials options for TSV etch, liner, and barrier/seed (B/S). For each of these options, recipes were adjusted for post-etch clean, ECD Cu fill and CMP overburden, and the resulting cost impacts were evaluated. The TSV dimensions used in this study are 5x50 μm and 2x40 μm. These cost comparisons included a sensitivity analysis, highlighting the main factors responsible for the differences. Cost of materials, tool cost, and throughput were the primary factors affecting cost differences, especially in barrier/seed deposition. In some cases the contributions from both these sources were comparable. We explain the assumptions used and some of the uncertainties inherent in this work. For example, where materials costs were significant, we extrapolated the cost of new materials from research quantities to those needed to support high volume manufacturing. We had to estimate throughputs and materials costs using our best engineering judgment, because the recipes have not yet been optimized. We also considered that the tools used on some non-critical steps might be fully depreciated, or a lower cost tool such as is used in wafer level packaging. Despite these uncertainties and assumptions, we were able to extract some fairly clear conclusions. The process options include the following B/S variations: For 5x50 μm TSVs, the B/S film structure is TaN/Ta/Ru/Cu, and the options are with and without the Ru and/or Cu layers. For 2x40 μm TSVs, the B/S structure is TaN/Ru/Cu, with different thicknesses of Ru, and the Cu is an optional seed layer for the field. We also discuss the impact of scaling the TSV dimensions on manufacturing costs. This work is continuing to look at different process options and to apply this methodology to MEOL modules such as temporary bond and debond, wafer thinning, and TSV reveal. Copyright © 2014 IMAPS - International Microelectronics Assembly and Packaging Society All Rights Reserved.

Di M.,University at Albany | Bersch E.,University at Albany | Clark R.D.,Technology Center America | Consiglio S.,Technology Center America | And 2 more authors.
Journal of Applied Physics | Year: 2010

Recent studies have shown that La2 O3 films can be used to adjust the threshold voltage (Vt) of NMOS Hf-based high-k/metal gate devices to desirable values, and a dipole at the high- k/ SiO2 interface has been proposed to explain the Vt shifts. In order to investigate the mechanism of the Vt shift further, we have measured the flatband voltage (Vfb) and Si band bending of technologically relevant TiN/ HfO2 / La2 O3 / SiO2 /p-Si stacks where the thickness and position of the La2 O 3 layer have been systematically varied. We observed systematic changes in Vfb, Si band bending and the HfO2 -Si valence band offset as a function of La2 O3 layer thickness and position. These changes can be explained by a band alignment model that includes a dipole at the high- k/ SiO2 interface, thus supporting the work of previous authors. In addition, we have derived the theoretical relationship between Vfb and Si band bending, which agrees well with our experimental measurements. © 2010 American Institute of Physics.

Bhuyian M.N.,New Jersey Institute of Technology | Misra D.,New Jersey Institute of Technology | Tapily K.,Technology Center America | Clark R.D.,Technology Center America | And 4 more authors.
ECS Transactions | Year: 2013

The reliability of atomic layer deposited Hf1-xZr xO2 with x=0.8 on a SiON interfacial layer (IL) has been analyzed in detail for three different oxide deposition processes, (i) DADA: samples were subjected to dielectric deposition and thermal annealing in a cyclical process; (ii) DSDS: samples were subjected to similar cyclical process with dielectric deposition and exposure to Ar plasma; and (iii) As-Dep: the dielectric for the control samples was deposited without any intermediate step. Capacitance-voltage and current-voltage characteristics of the MOS capacitors (MOSCAP) with metal gate (TiN), subjected to a constant field stress of 2.75 × 10 V/cm in the gate injection mode, show that the flat-band voltage shift (ΔVFB) and stress induced leakage current (SILC) below 100 s stress is the lowest for DSDS samples whereas the worst degradation was observed for DADA samples. However, identical degradation was observed in all sample types when stress was increased to 1000 s. Intermediate plasma exposure (DSDS process) seems to supress the oxide trap formation as it provides EOT downscaling ability and good reliability performance. The reliability characteristics, when compared with pure HfO2, seem to improve with the addition of ZrO2. © The Electrochemical Society.

Teh W.H.,Intel Corporation | Caramto R.,SEMATECH | Chidambaram T.,Albany State University | Wang W.,Albany State University | And 4 more authors.
IEEE Transactions on Semiconductor Manufacturing | Year: 2010

We report a process development route toward 300-mm production-worthy non-Bosch through-silicon-via (TSV) etch with critical dimensions between 15 μm and aspect ratios up to 20:1 for 3-D logic applications. The etch development was performed on an experimental alpha-tool: a magnetically enhanced capacitively coupled plasma etcher with a dipole ring magnet that aims to capture the strengths (anisotropicity, profile uniformity) while eliminating the weaknesses (scalloping, undercut, residues) of a nominal Bosch process. Key factors contributing to the control of sidewall taper and roughness, etched TSV volume and depth, mask undercut, local bowing effects, and within wafer (WIW) center-to-edge depth and profile uniformity were evaluated. TSVs with nominal sizes of 5×25 μm, 5×40 μm and 1×20μm with less than 1% WIW nonuniformity, negligible silicon scalloping/mask undercut, and good profile anisotropicity were developed. Up to 3 × 20 μm and 5 × 25 μm void-free Cu-filled TSVs were demonstrated with both vertical TSVs and tapered TSVs. © 2006 IEEE.

Tapily K.,Technology Center America | Ngai T.,Technology Center America | Clark R.D.,SEMATECH | O'Meara D.,Technology Center America | And 9 more authors.
ECS Transactions | Year: 2014

We report progress on surface passivation and functionalization of Ge channel surfaces, as well as high-k dielectric layer growth by atomic layer deposition (ALD) and the resulting electrical properties measured in transistor (MOSFET) and metal oxide semiconducting capacitor (MOSCAP) structures. Epitaxial Si and Al2O3 passivation of Ge show improved performance with 3 times reduction in interface states density (Dit), higher conductance, reduced hysteresis and sub-1nm EOT as opposed to non-passivated interface. A 3 times drive current improvement to Si MOSFET was achieved with thin Al2O3 passivation layer. © 2014 by The Electrochemical Society. All rights reserved.

Brcka J.,Fuller Inc. | Robison R.L.,Technology Center America
Modelling and Simulation in Engineering | Year: 2011

This contribution is dealing with experimental and computational evaluation of the deposition baffle that is transparent to radio frequency (RF) magnetic fields generated by an external antenna in an inductively coupled plasma (ICP) source but opaque to the deposition of the metal onto a dielectric wall in ionized physical vapor deposition (IPVD) system. Various engineering aspects related to the deposition baffle are discussed. Among the many requirements focus is on specific structure of the slots and analysis to minimize deposition on the baffle (we used a string model for simulating the profile evolution) and deposition through the DB on dielectric components of the ICP source. Transparency of the baffle to RF magnetic fields is computed using a three-dimensional (3D) electromagnetic field solver. A simple two-dimensional sheath model is used to understand plasma interactions with the DB slot structure. Performance and possible failure of device are briefly discussed. © 2011 J. Brcka and R. L. Robison.

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