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Kaplani E.,Technological Educational Institute of Patra
Journal of Engineering Science and Technology Review | Year: 2012

This paper presents ageing effects observed in sc-Si PV modules operating in field conditions for 18 and over 22 years. The effects of both natural ageing processes and induced ageing by external agents, causing partial or total shading of cells for a prolonged period of time, are examined. Optical degradation effects observed through visual inspection include discoloration of the EVA, degradation of the AR coating, degradation of the interface between the cell and encapsulant, corrosion of busbars and fingers, and tears, bubbles and humidity ingress at the back surface of the modules. Thermal degradation effects examined via IR thermography reveal the existence of hot cells, hotspots on the busbars, and colder bubbles. Modules' power and performance degradation is assessed through I-V curve analysis. Results show naturally aged modules to exhibit milder ageing effects than modules subjected to induced ageing, an outcome also supported by their power degradation ratio. ©2012 Kavala Institute of Technology. Source


Background: Recently, verb-noun processing differences were reported in a group of late bilingual speakers with fluent, anomic aphasia in Greek (L1) as well as in English (L2) (Kambanaros & van Steenbrugge, 2006). The findings revealed that verb production was significantly more impaired than noun production in both languages during picture naming despite preserved comprehension of action and object names. Aims: The aim of this study is to investigate the total number (quantity) and the diversity (quality or different types) of verbs and nouns produced in conversational speech by the same group of bilingual anomic individuals with aphasia and compare the results to (i) those of the non-brain-injured control group and (ii) their action and object naming performances at the single word level, to determine if grammatical class impairments are also evident in spontaneous speech. Methods & Procedures: In order to examine the distribution and diversity of verbs and nouns in spontaneous speech, speech samples of 300 words were collected from the bilingual individuals with fluent aphasia and their controls in L1 and in L2 on two separate occasions, 1 week apart. In addition, two subtests from the Greek Object and Action Test (GOAT: Kambanaros, 2003), the object and action naming subtests, were presented on two separate occasions, 1 week apart, to both groups of bilingual participants in L1 and L2 (cf. Kambanaros & van Steenbrugge, 2006). Outcomes & Results: Late bilingual participants with anomia showed no difficulties retrieving verbs in spontaneous speech in L1 or L2 despite a significant verb deficit in both languages on action naming tasks. However the bilingual group had significant difficulties in relation to noun production in spontaneous speech in L1 and L2. Conclusions: Picture naming remains the standard of word retrieval ability in aphasia. However, object and action naming scores can underestimate and/or overestimate word retrieval performance for nouns and verbs in connected speech. © 2010 Psychology Press. Source


Bisdounis L.,Technological Educational Institute of Patra
2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010 - Proceedings | Year: 2010

A considerable part of the energy dissipation in CMOS buffers is due to short-circuit currents. In this paper, an accurate, analytical and compact model for this part of energy, i.e. the short-circuit energy dissipation, is presented. The model is based on closed-form expressions of the CMOS inverter output waveform, which include the influences of both transistor currents and the gate-drain coupling capacitance. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100nm devices, with an extension for varying transistor widths. The resulting energy model accounts for the influences of input voltage transition time, transistors' sizes, device carrier velocity saturation and narrow-width effects, gate-drain and short-circuiting transistor's gate-source capacitances, and output load. The model has been validated for a 90-nm CMOS technology, for different input transition times, capacitive loads & inverter sizes. The results show very good agreement with BSIM4 HSPICE simulations. ©2010 IEEE. Source


Bikos A.N.,University of Patras | Sklavos N.,Technological Educational Institute of Patra
IEEE Security and Privacy | Year: 2013

The authors give an overview on the state of the art of potential security issues that occur in the deployment of the LTE/SAE (Long-Term Evolution/System Architecture Evolution) protocol in emerging 4G wireless technologies. Although security concerns and challenges in wireless networks will remain a hot topic in the future, the LTE/SAE standard could adapt to these rising challenges, becoming more robust and secure. By looking at the authentication and ciphering algorithms, such as EAP-AKA (Extensible Authentication Protocol for Authentication and Key Agreement), currently operating within the LTE protocol, the authors analyze several vulnerabilities in LTE/SAE security architecture-specifically, insecure AKA key derivation procedures and the lack of fast reauthentications during handovers. © 2003-2012 IEEE. Source


Bisdounis L.,Technological Educational Institute of Patra
Journal of Circuits, Systems and Computers | Year: 2011

Modeling of CMOS inverters and consequently, CMOS gates, is a critical task for improving accuracy and speed of simulation in modern sub-100 nm digital circuits. One of the key factors that determine the operation of a CMOS structure is the influence of the input-to-output coupling capacitance, also called overshooting effect. In this paper, an analytical model for this effect is presented, that computes the time period which is necessary to eliminate the extra output charge transferred through the input-to-output capacitance at the beginning of the switching process in a CMOS inverter. In addition, the maximum or minimum output voltage (depending on the considered edge) is analytically computed. The derived model is based on analytical expressions of the CMOS inverter output voltage waveform, which include the influences of both transistor currents and the input-to-output (gate-to-drain) coupling and load capacitances. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100 nm devices, with an extension for varying transistor widths. The resulting model also accounts for the influences of input voltage transition time, transistors' sizes, as well as device carrier velocity saturation and narrow-width effects. The results produced by the presented model for three sub-100 nm CMOS technologies, several input voltage transition times, capacitive loads and device sizes, show very good agreement with BSIM4 HSPICE simulations. © 2011 World Scientific Publishing Company. Source

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