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Bauer C.E.,TechLead Corporation | Fillion R.A.,TechLead Corporation | Neuhaus H.J.,TechLead Corporation
2010 12th Electronics Packaging Technology Conference, EPTC 2010 | Year: 2010

Advanced packaging conferences, technical articles, and editorials frequently focus on high pin count devices such as microprocessors and graphic processor devices. The substantial challenges incumbent on high I/O package designs warrant this attention. However, an entire universe of high performance packages with low pin counts also exist. Diodes, power transistors, RFIDs, engine controllers, and MEMs devices rarely demand more than eight terminals and often only require two. Almost all systems employ at least some low pin count devices. On the other hand, applications such as alternative energy equipment, LED lighting, automotive electronics, and ubiquitous sensor networks consist primarily of high performance, low pin count devices. In this paper the authors review families of applications that rely on high performance, low pin count devices and identify application-specific requirements such as power delivery, thermal management, signal integrity, and reliability. Next the paper analyzes the strengths and weaknesses of various packaging strategies, both traditional and emerging, developed for these applications. Specific package types considered include wire-bond, flip chip, hybrid, and embedded packaging as well as new approaches based on printed conductors, conductive adhesives, flexible substrates, and organic electronics. Finally, the authors assess the opportunities and challenges associated with packaging high performance, low pin count devices. ©2010 IEEE.

Neuhaus H.J.,Techlead Corporation | Fillion R.A.,Techlead Corporation | Bauer C.E.,Techlead Corporation
SMT Surface Mount Technology Magazine | Year: 2010

Strategic business decisions begin with assessments of market need, value proposition and differentiation, profit potential and sustainability. Predicting the future implies uncertainty and emerging markets often push forecasting into the realm of guesses and hunches. However, structured analysis of published patents and patent applications provides valuable insight into strategies, aspirations and expected competitive positions long before the first sale in an emerging market. Using MEMS packaging as an example, the authors show how in emerging markets pending patent applications often outnumber issued patents and then demonstrate how careful study of public databases for published patent applications yield a detailed picture of anticipated competitive environments, as well as quantification of market trends and growth expectations. Finally, the authors apply the IP landscaping method to developing a strategic framework useful for investment, market development and strategic alliance planning.

Bauer C.E.,TechLead Corporation | Neuhaus H.J.,TechLead Corporation
Proceedings - 2013 14th International Conference on Electronic Packaging Technology, ICEPT 2013 | Year: 2013

The evolutionary developments in integrated circuits predicted by Moore's Law apply steady pressure on packaging, interconnect, and assembly to deliver finer geometry. As conventional technology, such as subtractive PWB patterning and chips-last assembly, approaches performance, cost and yield barriers, innovative approaches become competitive in spite of potential infrastructure disruptions. In particular, the notion of embedding traces and devices within the interconnect substrate has emerged as an attractive yet unconventional means to achieving fine geometry systems. Innovative concepts in embedded technology lead the way to miniaturization, cost reduction and performance enhancement. For example, Imprint Patterning (IP) buries traces to enable padless designs and maskless soldering with a variation of the stamper technology employed in CD and DVD production. Remarkably, IP delivers these benefits at higher yield and lower cost than conventional board processes. Similarly, Chips-First assembly enables superior electrical performance and thermal management by embedding devices and adding interconnect afterwards. Inherently scalable, Chips-First assembly replaces wire-bonds and solder bumps with direct metallurgical connections to the chip. Finally, Capillary Chip Connection (C3) allows fine pitch joining with reduced electrical parasitics by replacing solder balls with minute solder menisci. This paper reviews these three embedded approaches to fine geometry and assesses their outlook and opportunities with particular attention to potential infrastructure disruptions and business model concerns. © 2013 IEEE.

Bauer C.E.,TechLead Corporation | Fillion R.A.,TechLead Corporation | Neuhaus H.J.,TechLead Corporation | Papageorge M.,Semiconductor Outsourcing Solutions
Proceedings of the ASME InterPack Conference 2009, IPACK2009 | Year: 2010

Early MEMS devices employed packages developed for conventional semiconductor microelectronics. Today, MEMS packages reflect the unique environment, mechanical, chemical and thermal requirements of MEMS devices themselves. A casual search of on-line databases reveals nearly 40,000 patents worldwide containing the words "MEMS" and "package." While not all relevant, the number of IP documents easily overwhelms researchers, investors and IP practitioners. The authors systematically analyze the relevant IP and organize it by generic technology categories. A unique mapping methodology provides greater understanding of the landscape of IP in the MEMS packaging arena across a wide range of considerations including geography, IP development and ownership trends, infrastructure implications and application concepts. The authors also present a rudimentary valuation of IP within the MEMS packaging field based on citation analysis. Finally, the authors demonstrate a method to develop a strategic framework based on the IP landscape useful for investment, market development and strategic alliance planning. Copyright © 2009 by ASME.

Bauer C.E.,TechLead Corporation | Neuhaus H.J.,TechLead Corporation
Microelectronics Reliability | Year: 2013

Embedding active and passive components in an interconnect substrate offers improved performance by cutting interconnect parasitics, reliability gains through elimination of wire-bonds and solder-bumps, and reduced cost and size via parts list reduction. Like every new development, these benefits come at a price: disrupted supply chain logistics, yield management complications and limited rework and repair options. Reliability considerations for embedded components include yield management strategies, WEEE and ROHS compliance, application specific life expectancy, and supply chain restructuring. The course also covers cost and warranty implications and concludes reviewing the drivers behind embedded active and passive components along with analysis of multiple examples in today's real life embedded component applications. © 2013 Elsevier Ltd. All rights reserved.

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