Hsinchu, Taiwan

Taiwan Semiconductor Manufacturing Company, Limited , also known as Taiwan Semiconductor, is the world's largest dedicated independent semiconductor foundry, with its headquarters and main operations located in the Hsinchu Science and Industrial Park in Hsinchu, Taiwan. Wikipedia.


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Patent
Taiwan Semiconductor Manufacturing Company | Date: 2016-08-22

A multiple-port memory cell includes first conductive lines in a first metal layer, second conductive lines in a second metal layer, third conductive lines a third metal layer, and fourth conductive lines in a fourth metal layer. The first conductive lines include a write bit line electrically coupled with a write bit line node; a first read bit line electrically coupled with a first read bit line node; and a second read bit line electrically coupled with a second read bit line node. The second conductive lines include a write word line electrically coupled with a write word line node. The fourth conductive lines include a first read word line electrically coupled with a first read word line node; and a second read word line electrically coupled with a second read word line node.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2016-08-16

Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2016-08-18

Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2016-08-16

A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2016-08-16

Presented herein is a device processing boat comprising a base and at least one unit retainer disposed in the base. The device further comprises a cover having at least one recess configured to accept and retain at least one unit. The at least one recess is aligned over, and configured to hold the at least one unit over, at least a portion of the at least one unit retainer. The cover is retained to the device processing boat by the at least one unit retainer. At least one pressure sensor having at least one sensel is disposed in the base. The sensel is configured to sense a clamping force applied by the cover to the at least one unit.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2016-08-22

A method for performing contactless signal testing includes receiving, with a testing pad of an integrated circuit, a signal within a beam. The method further includes converting, with a number of diodes connected to a positive voltage supply, an electrical current signal created by the electron beam to a voltage signal, wherein the number of diodes includes a diode stack of multiple diodes. The method further includes extracting, with a digital inverter, a test signal from the voltage signal.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2016-08-23

According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2016-02-02

In some embodiments, a circuit includes a first transistor, a second transistor, a resistive device and an amplifier. The first transistor includes a first drain and a first gate. The second transistor includes a second drain and a second gate. The resistive device is coupled between the first gate and the second gate. The amplifier includes a first input coupled to the first drain and a second input coupled to the second drain. The amplifier is configured to keep a voltage level at the first drain and that at the second drain equal to each other.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2016-09-07

The present disclosure relates to an integrated chip having a multiband transmission and reception elements coupled to an integrated dielectric waveguide. In some embodiments, the integrated chip has a dielectric waveguide disposed within an inter-level dielectric (ILD) structure over a substrate. A multiband transmission element having a plurality of phase modulation elements is configured to generate a plurality of modulated signals in different frequency bands. A plurality of transmission electrodes are located along a first side of the dielectric waveguide and are respectively configured to couple one of the plurality of modulated signals into the dielectric waveguide.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2016-09-09

A process of an extreme ultraviolet lithography is disclosed. The process includes receiving an extreme ultraviolet (EUV) mask, an EUV radiation source and an illuminator. The process also includes exposing the EUV mask by a radiation, originating from the EUV radiation source and directed by the illuminator, with a less-than-three-degree chief ray angle of incidence at the object side (CRAO). The process further includes removing most of the non-diffracted light and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target.

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