Taiwan Semiconductor Manufacturing Company

www.tsmc.com
Hsinchu, Taiwan

Taiwan Semiconductor Manufacturing Company, Limited , also known as Taiwan Semiconductor, is the world's largest dedicated independent semiconductor foundry, with its headquarters and main operations located in the Hsinchu Science and Industrial Park in Hsinchu, Taiwan. Wikipedia.

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Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-01-06

In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by forming an initial conductive filament within a dielectric data storage layer of an RRAM cell having a bottom electrode connected to a drain terminal of a PMOS transistor and a top electrode separated from the bottom electrode by the dielectric data storage layer. The initial conductive filament is formed by turning on the PMOS transistor by providing a substantially zero first forming voltage to a gate terminal of the PMOS transistor, by providing a substantially zero second forming voltage to a source terminal of the PMOS transistor, by providing a first non-zero forming voltage to a bulk terminal of the PMOS transistor, and by providing a second non-zero forming voltage to the top electrode.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-01-30

A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-01-30

A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-01-30

A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-01-27

In accordance with an embodiment a method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-01-27

A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by one or more shared flexible membranes. The method also includes setting a first profile of the surface of the first wafer chuck. Setting a first profile of the surface of the first wafer chuck includes adjusting a first volume of a first profile control zone of the multiple first profile control zones. Setting a first profile of the surface of the first wafer chuck also includes adjusting a second volume of a second profile control zone of the multiple first profile control zones, the first volume of the first profile control zone being adjusted independently from the second volume of the second profile control zone, and the second adjustable volume encircling the first adjustable volume.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-01-27

A semiconductor device is provided. The semiconductor device includes a first fin partially surrounded by a first isolation structure and a second fin partially surrounded by a second isolation structure. The second isolation structure has a dopant concentration higher than that of the first isolation structure, and a height difference is between a top surface of the first isolation structure and a top surface of the second isolation structure.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-01-30

The present disclosure relates to an integrated circuit configured to mitigate damage to MIM decoupling capacitors. In some embodiments, the integrated chip has a lower metal interconnect layer arranged over a substrate. A plurality of MIM (metal-insulator-metal) structures are arranged over the lower metal interconnect layer, and a plurality of memory cells are arranged over the lower metal interconnect layer at a location laterally offset from the plurality of MIM structures. An upper metal interconnect layer is arranged over the plurality of MIM structures and the plurality of memory cells. One or both of the lower metal interconnect layer and the upper metal interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection. The plurality of MIM structures and the plurality of memory cells comprise multi-layer structures having a substantially same shape.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-01-30

A method of forming a semiconductor device includes forming a passivation layer on top of a guard ring and an active area of a circuit device, forming a passivation contact within the passivation layer, the passivation contact being over and electrically connected to the guard ring, forming a post-passivation interconnect (PPI) guard ring over the passivation layer and electrically connected to the passivation contact, and forming a first polymer layer over the PPI guard ring, the first polymer layer extending along a sidewall of the PPI guard ring.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-01-27

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

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