Hsinchu, Taiwan

Taiwan Semiconductor Manufacturing Company, Limited , also known as Taiwan Semiconductor, is the world's largest dedicated independent semiconductor foundry, with its headquarters and main operations located in the Hsinchu Science and Industrial Park in Hsinchu, Taiwan. Wikipedia.


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Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-02-02

A circuit includes a time delta detector configured to receive an input clock signal and a reference clock signal and generate a delta pulse signal and a reference pulse signal. A comparison circuit is configured to receive the delta pulse signal and the reference pulse signal. The comparison circuit generates an output indicative of a bit of a time difference between the input clock signal and the reference clock signal. A control circuit is configured to receive the output from the comparison circuit. The control circuit maintains a count of the time difference between the input clock signal and the reference clock signal.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-02-02

A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-02-03

A memory device comprises a tracking control circuit for controlling the write operation or the read operation of the memory device. The tracking control circuit comprises a plurality of tracking cells, wherein the timing characteristics of the tracking cells emulate the timing characteristics of a bit cell during a write operation or a read operation of the memory device. The memory device further comprises at least two reference word lines for configuring the number of tracking cells of the tracking control circuit; and a selection circuit configured to activate one or more of the at least two reference word lines.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-02-06

A static random access memory (SRAM) chip includes a first and second conductor, a set of SRAM cells and a set of first and second tracking cells. The first conductor extends in a first direction, is coupled to a first supply voltage, and on a first metal layer. The second conductor extends in a second direction, is coupled to a second supply voltage, and on a second metal layer. A first cell of the set of first tracking cells includes a first tracking bit line conductor, first and second CMOS, and a first and second pass gate device. A first cell of the set of second tracking cells includes a third pass gate device, a third PU device, and a third PD device having a source configured to be electrically floating. A gate of the first PD device or the first PU device is electrically coupled to the first conductor.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-02-02

A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured to generate a reference current for reading data stored in the memory cell. The reference signal generator includes a first circuit coupled to a current summation node and having a reference cell. The first circuit is configured to generate a first current that flows between drain and source terminals of a transistor in the reference cell. The reference signal generator also includes a second circuit coupled to the current summation node and configured to generate a second current that is a temperature-dependent current. The current summation node is configured to combine the first and second currents to generate the reference current that tracks a temperature trend of a current flowing through the memory cell.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-02-06

Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-02-03

Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-02-06

A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-02-06

A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.


Patent
Taiwan Semiconductor Manufacturing Company | Date: 2017-02-08

Provided is a method of fabricating a semiconductor device. An integrated circuit (IC) layout plan is obtained, The IC layout plan contains critical features and non-critical features. Locational information regarding a defect on a blank reticle is obtained. The blank reticle is a candidate reticle for being patterned with the IC layout plan. Based on the locational information regarding the defect and the IC layout plan, a determination is made that at some of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan, regardless of whether the IC layout plan is globally manipulated or not before being patterned onto the blank reticle. In response to the determination, selected local portions of the IC layout plan are re-arranged such that none of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan.

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