Entity

Time filter

Source Type


Biallas S.,RWTH Aachen | Brauer J.,Verified Systems International GmbH | Kowalewski S.,RWTH Aachen
2012 27th IEEE/ACM International Conference on Automated Software Engineering, ASE 2012 - Proceedings | Year: 2012

This paper introduces Arcade.PLC, a verification platform for programmable logic controllers (PLCs). The tool supports static analysis as well as ∀CTL and past-time LTL model checking using counterexample-guided abstraction refinement for different programming languages used in industry. In the underlying principles of the framework, knowledge about the hardware platform is exploited so as to provide efficient techniques. The effectiveness of the approach is evaluated on programs implemented using a combination of programming languages. Copyright 2012 ACM. Source


Loding H.,Verified Systems International GmbH | Peleska J.,University of Bremen
ICST 2010 - 3rd International Conference on Software Testing, Verification and Validation | Year: 2010

In this paper we introduce Timed Moore Automata, a specification formalism which is used in industrial train control applications for specifying the real-time behavior of cooperating reactive software components. We define an operational semantics for the sequential components (units) with an abstraction of time that is suitable for checking timeout behavior of these units. A model checking algorithm for livelock detection is presented, and two alternative methods of test case/test data generation techniques are introduced. The first one is based on Kripke structures as used in explicit model checking, while the second method does not require an explicit representation but relies on SAT solving techniques. © 2010 IEEE. Source


Gunther H.,TU Braunschweig | Milius S.,TU Braunschweig | Moller O.,Verified Systems International GmbH
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Year: 2012

Large asynchronous systems composed from synchronous components (so called GALS-globally asynchronous, locally synchronous-systems) pose a challenge to formal verification. We present an approach which abstracts components with contracts capturing the behavior by a mixture of temporal logic formulas and non-deterministic state machines. Formal verification of global system properties is then done transforming a network of contracts to model checking tools such as Promela/SPIN or UPPAAL. Synchronous components are implemented in Scade, and contract validation is done using the Scade Design Verifier for formal verification. We also discuss first experiences from an ongoing industrial case study applying our approach. © 2012 Springer-Verlag. Source


Reinbacher T.,Vienna University of Technology | Fugger M.,Vienna University of Technology | Brauer J.,Verified Systems International GmbH | Brauer J.,RWTH Aachen
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Year: 2013

We present an algorithmic framework that allows on-line monitoring of past-time MTL specifications in a discrete time setting. The algorithms allow to be synthesized into efficient observer hardware blocks, which take advantage of the highly-parallel nature of hardware designs. For the time-bounded Since operator of past-time MTL we obtain a time complexity that is double logarithmic in the time it is executed at and the given time bounds of the Since operator. This result is promising with respect to a non-interfering monitoring approach that evaluates real-time specifications during the execution of the system-under-test. The resulting hardware blocks are reconfigurable and have applications in prototyping and runtime verification of embedded real-time systems. © 2013 Springer-Verlag Berlin Heidelberg. Source


Brauer J.,RWTH Aachen | Brauer J.,Verified Systems International GmbH | King A.,Portcullis Computer Security Ltd | Kowalewski S.,RWTH Aachen
Science of Computer Programming | Year: 2013

Bitwise instructions, loops and indirect data access present challenges to the verification of microcontroller programs. In particular, since registers are often memory mapped, it is necessary to show that an indirect store operation does not accidentally mutate a register. To prove this and related properties, this article advocates using the domain of bitwise linear congruences in conjunction with intervals to derive accurate range information. The paper argues that these two domains complement one another when reasoning about microcontroller code. The paper also explains how SAT solving, which applied with dichotomic search, can be used to recover branching conditions from binary code which, in turn, further improves interval analysis. © 2011 Elsevier B.V. All rights reserved. Source

Discover hidden collaborations