Systems Reliability Group

Bangalore, India

Systems Reliability Group

Bangalore, India
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Desai K.,Systems Reliability Group | Manasa B.,Systems Reliability Group | Chetwani R.,Systems Reliability Group | Bhanumathy Y.R.,Systems Reliability Group | Ravindra M.,Systems Reliability Group
2016 5th International Conference on Reliability, Infocom Technologies and Optimization, ICRITO 2016: Trends and Future Directions | Year: 2016

ISRO Satellite Centre (ISAC) is the lead centre for development and operationalisation of communication, remote sensing and interplanetary missions. These satellites contain highly advanced embedded systems carrying out critical operations thus achieving mission goals. In the ISRO's current generation of spacecrafts, as autonomy taking the centre stage, complexity of spacecrafts have increased manifold. Attitude and Orbit Control Electronics (AOCE), is one of the main subsystems where most of the autonomy features are implemented. To handle autonomy functionalities, Electrically Erasable and Programmable Read Only Memory Management (EEPROM) is interfaced with AOCE On board software. On-board autonomy functions use data and logics stored in EEPROM memory via onboard software. Testing these interface logics had an inherent constraint in performing number of write operations on EEPROM device[1]. Overcoming this limitation and performing exhaustive testing of autonomy and EEPROM interface logics was a challenge. Simulation based test facility was already established to test all on-board software functionalities. Hence, EEPROM memory device had to be simulated and interfaced with this test facility, in order to test on-board autonomy functions. In addition, along with EEPROM, other memory devices like, Storage Random Access Memory (RAM) and Programmable Read Only Memory (PROM) are used for various critical functionalities. Having a device specific simulation model for EEPROM, Storage RAM and Programmable Read Only Memory (PROM) although technically feasible, lacks software reusability, thereby increasing development and testing time. To make the memory controller simulation more generic and reusable object oriented methodology was used [2]. The design model described in the rest of the paper provides an overview of the same. This paper focuses, mainly on the design methodology used to simulate EEPROM as a case study. This paper also discusses in brief the results obtained by testing using this simulation technique and advantages reaped from the same. © 2016 IEEE.

Shankar S.S.,Systems Reliability Group | Desai K.,Systems Reliability Group | Dutta S.,Systems Reliability Group | Chetwani R.R.,Systems Reliability Group | And 2 more authors.
Proceedings of 2014 International Conference on Contemporary Computing and Informatics, IC3I 2014 | Year: 2014

ISRO Satellite Centre (ISAC) is the lead centre of the Indian Space Research Organisation in the development and operationalisation of satellites for communication, navigation and remote sensing applications. In all these spacecrafts, highly advanced embedded systems carryout variety of mission critical functions. Each of these embedded systems house heterogeneous Processor and Embedded Software Combinations to carry out their functionalities. As per existing practices, testing of on board software to confirm its functioning takes place only when the software is integrated with its associated hardware. On the contrary, by a technique called the Software in Loop Simulation (SILS) test method, the on-board software can be fully tested in a software simulated dynamic environment without Hardware. This method of flight software validation is demonstrated in MARS ORBITER MISSION for AOCE, TCP, SSR, BDH software. The results very well demonstrate the effectiveness of the technique in early performance prediction and assessment of on-board software. This validation philosophy will be followed for all future spacecrafts. In a development environment where software requirements are too complex and requirement changes are to be incorporated even during final stages of development, this technique offers an excellent solution in fully validating on board software at source code level before it gets integrated with target hardware. This additional validation step not only improves software quality but also enhances productivity and reduces system turnaround time. © 2014 IEEE.

Agarwal R.,Systems Reliability Group | Chetwani R.R.,Systems Reliability Group | Ravindra M.,Systems Reliability Group | Bharadwaj K.M.,Reliability and Components Area
2014 International Conference on Advances in Electronics, Computers and Communications, ICAECC 2014 | Year: 2015

This paper focuses on requirements to design traceability. There have been many advances in requirements traceability and various tools are available to perform requirements traceability. Software Requirements to Design Traceability Technique named SoRDeTT, is the methodology proposed, which is based on templates. Software Requirements Specification (SRS) and Software Design Document (SDD) form inputs to this methodology. SoRDeTT has defined a common template (for requirement and design) to capture data and information from these documents. The template with data populated from SRS is called SRS Trace Item (SRSTI), and the one filled with data from SDD is called SDD Trace Item (SDDTI). The template defined needs to be filled for every software requirement. Initialization, input, output, data type, range, resolution of data etc. are the fields which are part of the template. The filled templates namely SRSTI and SDDTI corresponding to all software requirements are used to carry out traceability analysis. Since the template is same for requirements and design data, hence it is easy to compare and raise alerts for appropriate action to be taken. © 2014 IEEE.

Athiray P.S.,Space Astronomy Group | Athiray P.S.,University of Calicut | Narendranath S.,Space Astronomy Group | Sreekumar P.,Space Astronomy Group | And 2 more authors.
Planetary and Space Science | Year: 2013

The Chandrayaan-1 X-ray Spectrometer (C1XS) observed characteristic X-ray fluorescence (XRF) lines of major rock forming elements from the lunar surface during different solar flare conditions. As the Sun was undergoing an unusually low activity cycle during the observing period of C1XS (28th Nov. 2008-29th Aug. 2009), most observations were made during weak flares. To derive the lunar surface chemistry, observed XRF line fluxes were converted to corresponding elemental abundances. Line flux dependencies like incident solar spectra (I o), geometry of observation and matrix effects are taken into consideration while converting line fluxes to abundances. We describe our approach which uses the concept of flux fraction to derive abundances of major elements (weight percentages >1%). The standard Fundamental Parameter (FP) method is employed. The paper also discusses the validation of our method using laboratory experiments with samples of known composition. We demonstrate our ability to derive elemental abundances with only a few wt% errors from remote sensing data. © 2012 Elsevier Ltd.

Varaprasad R.,Systems Reliability Group | Gnanasambanthan R.,Systems Reliability Group | Ravikumar J.V.N.,Systems Reliability Group | Pamireddy C.J.R.,Systems Reliability Group | And 3 more authors.
IEEE Aerospace and Electronic Systems Magazine | Year: 2014

In general, space transportation systems are expendable, resulting in huge launch cost. To meet the future challenge of low-cost access to space, the Indian Space Research Organisation (ISRO) envisaged plans to develop systems that are recoverable and reusable, besides adopting effcient propulsion systems like air-breathing rockets. Advanced Technology Vehicle (ATV) D01 is ISRO's new-generation high-performance sounding rocket vehicle offering a cost-effective test bed for demonstrating air-breathing propulsion. Experiments with scramjet technology testing are carried out at Satish Dhawan Space Centre (SDSC) SHAR, Sriharikota. For this experiment, ATV-D01 is confgured as a two-stage, un-guided, spinning, fn-stabilized vehicle with two protruding passive scramjet engines. © 1986-2012 IEEE.

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