Mountain View, CA, United States
Mountain View, CA, United States

Synopsys, Inc., an American company, is the leading company by sales in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit. Products include logic synthesis, behavioral synthesis, place and route, static timing analysis, formal verification, HDL simulators as well as transistor-level circuit simulation. The simulators include development and debugging environments which assist in the design of the logic for chips and computer systems. Wikipedia.


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Patent
Synopsys Inc. | Date: 2017-01-25

A method to program bitcells (11, ..., mn) of a ROM array (10) uses different programming cells (0a, ..., 0h, 1a, ..., 1d) for programming the bitcells (11, ..., mn) with a first or second data item. A first bitcell (11) is programmed by means of a selected programming cell, wherein the programming cell is selected in dependence on operating the memory array (10) as a flipped or a non-flipped memory in multi-bank instance. All other bitcells (12, 13) located in the same column (C1) as the first bitcell (11) and subsequent rows (R2, R3) are programmed by selected programming cells, wherein the selection of the programming cells is dependent on operating the memory array (10) as a flipped or a non-flipped memory in multi-bank instance and the programming state of the programming cells used for the previously programmed bitcells in the same column (C1).


Patent
Synopsys Inc. | Date: 2017-01-24

A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated.


Patent
Synopsys Inc. | Date: 2017-01-23

A method and system for detecting tampering of authenticated memory blocks that are accessible by an untrusted host processor, by (1) periodically re-authenticating the memory blocks from a trusted computing environment, and (2) disabling accessing of the memory blocks by the untrusted host processor when the re-authenticating fails. In one implementation, each of the memory blocks has an authentication code, and the accessing of the memory blocks is disabled by disabling the untrusted host processor. The memory blocks may be re-authenticated sequentially, or randomly, e.g., based on a random block selection based on the block location, or based on temporal randomness. The re-authenticating is preferably effected by an authentication module in the trusted computing environment.


Patent
Synopsys Inc. | Date: 2017-01-13

A system-level simulation includes generating netlist information including component library information, which describes instances of the hardware components, and component instance information, which describes component dynamic libraries that include models of hardware components. The simulation is generated at simulation run-time based on the netlist information. Component dynamic libraries corresponding to the component library information are loaded based on the component library information. A simulation dynamic library referenced by the component dynamic libraries is loaded. One or more interlibrary adapters corresponding to the component dynamic libraries are loaded to provide compatibility between the component dynamic libraries and an application binary interface of the simulation dynamic library. Instances of hardware components are instantiated based on the component instance information, and the instantiated instances of the hardware components are connected to form the simulation. The simulation is performed at simulation run-time responsive to the simulation being generated.


Patent
Synopsys Inc. | Date: 2017-01-13

Systems and techniques for alleviating congestion are described. A set of buffer chains that pass through a congested region of the circuit design can be identified. Next, the set of the buffer chains can be removed from the circuit design. A placement blockage in the circuit design can then be created that covers at least a portion of the congested region. Next, the buffer chains that were removed can be reconstructed in the circuit design in the presence of the placement blockage, thereby alleviating congestion. Once the buffer chains have been reconstructed, the placement blockage can be removed from the circuit design. In some embodiments, congestion can be alleviated by spreading out buffer chains based on spreading out center of mass lines corresponding to the buffer chains.


A system for reseeding a pseudo random number generator to generate pseudo random numbers includes a true random number generator generating a true random number, a storage device storing the generated true random number, a pseudo random number generator generating pseudo random numbers using the stored true random number as a seed, and a controller coupled to the true random number generator and the pseudo random number generator to (1) generate a new true random number concurrently with the operation of the pseudo random number generator, and storing the new true random number, and (2) reseed the pseudo random number generator with the new true random number.


An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the circuit is described.


Patent
Synopsys Inc. | Date: 2017-04-19

A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.


An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The number of nanowires or 2D material strips in the first set can be different from the number of nanowires or 2D material strips in the second set, so that the drive power of the individual transistors can be set with finer granularity.


An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a memory cell including a plurality of transistors, at least some of the transistors in the plurality having channels comprising respective sets of one or more nanowires or 2D material strips, and wherein the channel of one of the transistors in the plurality has a different number of nanowires or 2D material strips than a channel of another transistor in the plurality. An integrated circuit including the memory cell is described.

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