Mountain View, CA, United States
Mountain View, CA, United States

Synopsys, Inc., an American company, is the leading company by sales in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit. Products include logic synthesis, behavioral synthesis, place and route, static timing analysis, formal verification, HDL simulators as well as transistor-level circuit simulation. The simulators include development and debugging environments which assist in the design of the logic for chips and computer systems. Wikipedia.


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An automated circuitry that can co-exist in any chip and that allows for a accurate characterization of I*R drops at a block and/or whole chip level is described.


Patent
Synopsys Inc. | Date: 2016-10-31

A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.


Patent
Synopsys Inc. | Date: 2016-01-30

Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value (the enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction).


Patent
Synopsys Inc. | Date: 2016-08-03

Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.


Patent
Synopsys Inc. | Date: 2016-09-28

A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.


Patent
Synopsys Inc. | Date: 2016-12-08

Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.


Patent
Synopsys Inc. | Date: 2016-09-16

Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.


Patent
Synopsys Inc. | Date: 2016-12-05

Embodiments relate an emulation environment that places debugging logic in a manner that connections between the debugging logic and logic components outputs can be efficiently routed. In one embodiment, the host system places the debugging logic after placing the logic components of the DUT, but before routing the logic components. In another embodiment, the host system places debugging logic after placing and routing logic components of the DUT. In another embodiment, for one or more emulator FPGAs, the host system places debugging logic units of the debugging logic evenly across the FPGA before placing logic components of the DUT.


Patent
Synopsys Inc. | Date: 2017-01-25

A method to program bitcells (11, ..., mn) of a ROM array (10) uses different programming cells (0a, ..., 0h, 1a, ..., 1d) for programming the bitcells (11, ..., mn) with a first or second data item. A first bitcell (11) is programmed by means of a selected programming cell, wherein the programming cell is selected in dependence on operating the memory array (10) as a flipped or a non-flipped memory in multi-bank instance. All other bitcells (12, 13) located in the same column (C1) as the first bitcell (11) and subsequent rows (R2, R3) are programmed by selected programming cells, wherein the selection of the programming cells is dependent on operating the memory array (10) as a flipped or a non-flipped memory in multi-bank instance and the programming state of the programming cells used for the previously programmed bitcells in the same column (C1).


Grant
Agency: Cordis | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-06-2015 | Award Amount: 38.85M | Year: 2015

The goal of the PRIME project is to establish an open Ultra Low Power (ULP) Technology Platform containing all necessary design and architecture blocks and components which could enable the European industry to increase and strengthen their competitive and leading eco-system and benefit from market opportunities created by the Internet of Things (IoT) revolution. Over 3 years the project will develop and demonstrate the key building blocks of IoT ULP systems driven by the applications in the medical, agricultural, domestics and security domains. This will include development of high performance, energy efficient and cost effective technology platform, flexible design ecosystem (including IP and design flow), changes in architectural and power management to reduced energy consumption, security blocks based on PUF and finally the System of Chip and System in Package memory banks and processing implementations for IoT sensor node systems. Developped advanced as 22nm FDSOI low power technologies with logic, analog, RF and embedded new memory components (STT RAM and RRAM) together with innovative design and system architecture solutions will be used to build macros and demonstrate functionality and power reduction advantage of the new IoT device components. The PRIME project will realize several demonstrators of IoT system building blocks to show the proposed low power wireless solutions, functionality and performance of delivered design and technology blocks. The consortium semiconductor ecosystem (IDMs, design houses, R&D, tools & wafer suppliers, foundries, system/product providers) covers complementarily all desired areas of expertise to achieve the project goals. The project will enable an increase in Europes innovation capability in the area of ULP Technology, design and applications, creation of a competitive European eco-system and help to identify market leadership opportunities in security, mobility, healthcare and smart cost competitive manufacturing.

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