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Patil P.P.,SVIT Chincholi | Hatkar A.A.,SVIT Chincholi
1st IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems, ICPEICES 2016 | Year: 2016

The Carry Skip Adder (CSKA) is identified by a better efficiency in the trade off between operating speed and power dissipation, as it has a very low power-delay product, near to that of a carry-look ahead adder (CLA). A CSKA consists of blocks of full adder combined together, whose schematic (i.e., combination of full adders per block) mainly affects the overall operating speed of carry skip adder. These FA blocks are interconnected through 2/1 multiplexers. Worst case delay can be reduced with different techniques which has been proposed for full adders, this paper provides an optimization technique only for the case of constant block size to improve the speed performance. The addition operations will result in sum value and carry value. In general, addition is a process which involves two numbers which are added and carry will be generated. The addition operations will result in sum value and carry value. In this paper, the performance parameters of delay, average power, PDP and EDP are compared at different technology node. © 2016 IEEE.


Patil P.P.,SVIT Chincholi | Mahajan R.S.,SVIT Chincholi | Hatkar A.A.,SVIT Chincholi
2016 International Conference on Computer Communication and Informatics, ICCCI 2016 | Year: 2016

Adders are digital components which are widely in the digital integrated circuit design and are the important part of all digital applications like Digital Signal Processing (DSP), microprocessor applications. As the technology is scaling down, researchers are trying to design adders which are either high speed, low power consumption, less area. In this paper, the design of Ripple Carry Adder are discussed and are compared on the basis of their performance parameters such as area, delay and power distribution at 32nm and 45nm technology node has been compared. It is observed that the 32nm technology node even in all the parameters like delay area average power, power delay product, energy delay product gives better results. All the work has been carried out in Hspice software. © 2016 IEEE.

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