Zhao Q.,Suzhou Institute for Advanced Study of USTC |
Ip H.H.S.,City University of Hong Kong
Pattern Recognition Letters | Year: 2013
The paper presents a novel unsupervised contextual spectral (CSE) framework for human action and video classification. Similar to textual words, the visual word (a mid-level semantic) representation of an image or video contains a combination of synonymous words which give rise to the ambiguity of the representation. To narrow the semantic gap between visual words (mid-level semantic representation) and high-level semantics, we propose a high level representation called approximate-semantic descriptor. The experimental results show that the proposed approach for visual words disambiguation could improve the subsequent classification performance. In the paper, the approximate-semantic descriptor learning is formulated as a spectral clustering problem, such that semantically associated visual words are placed closely in low-dimensional semantic space and then clustered into one approximate- semantic descriptor. Specifically, the high level representation of human action videos is learnt by capturing the inter-video context of mid-level semantics via a non-parametric correlation measure. Experiments on four standard datasets demonstrate that our approach can achieve significantly improved results with respect to the state of the art, particularly for unconstrained environments. © 2013 Elsevier B.V. All rights reserved.
Zhou J.,Suzhou Institute for Advanced Study of USTC |
Wang C.,Suzhou Institute for Advanced Study of USTC
International Journal of Computational Science and Engineering | Year: 2015
Naive hash table (NHT) scheme associates a set of keys to a set of values. Apart from hash address computation, the search operation of the traditional scheme still brings three parts of overhead: key storage overhead, key memory access overhead, as well as key comparison overhead. They are significant especially when the hash table is too large to be implemented in slow off-chip memory. Therefore how to efficiently store keys in hash table is still posing serious challenges to researchers. In this paper, we propose a fast approximate hash table (FAHT) scheme which can eliminate these three parts of overhead with very small false rate. Theoretical analysis and data simulation are presented. The experiment results show that, with the same configuration, when the size of key is 128 bytes, FAHT uses 79% less memory than the NHT used, and if the hash address computation time is ignored, the speedup of FAHT comparing with NHT can be 199. Copyright © 2015 Inderscience Enterprises Ltd.
Zhu Z.,Hefei University of Technology |
Zhu Z.,Suzhou Institute for Advanced Study of USTC |
Wang J.,Hefei University of Technology |
Wang J.,Suzhou Institute for Advanced Study of USTC |
And 8 more authors.
Journal of Computational Information Systems | Year: 2014
Swapping read-ahead scheme plays a major role in virtual memory management, which is introduced to accelerate system performance by prefetching pages from external storage devices into main memory. Nowadays, the rapid evolving Solid-State Drive (SSD) technology starts to replace hard disk (HDD) due to its high speed. Traditional Linux's read-ahead policy is aimed at HDD and then numerous works have been proposed to exploit SSD's ash physical characteristics, such as abandoning ash translation layer and introducing the large ash block. However, previous works may ignore the impacts of multi-core system on read-ahead mechanism. Since more and more threads are parallel to run so that pages are randomly distributed in disk, traditional swapping read-ahead scheme takes HDD's sequential read speed advantage, but it may decrease the swap cache hit ratio and bring an awful performance for multi-core system. In this paper, we propose a novel thread-aware swapping read-ahead algorithm (TASR) for multi-core platforms with SSD architecture whose key idea is prefetching current running thread's pages rather than sequential system's pages. After numerous extensive experiments, emulation results demonstrate that our mechanism could reduce the swap cache miss ratio from 2.3% to 23.2% under multi-core environment, and real platform experiments confirms the emulation analysis results. Copyright © 2014 Binary Information Press.