Norcross, GA, United States
Norcross, GA, United States

Suniva Inc. is a U.S. manufacturer of high-efficiency silicon solar cells and high-power solar modules. Suniva's corporate headquarters and manufacturing plant, with a capacity of 170 MW, are located in Norcross, Georgia. Wikipedia.


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The invention relates to a solar cell and to a method of manufacturing a solar cell. The method comprises:forming a rectifying junction, with a first half and a second half, in a first semiconductor which can generate electrical current upon exposure to solar radiation;forming a first contact with ohmic electrical contact to the first half;forming a first alloy of a first metal and a first dopant, wherein the first dopant is capable of doping a semiconductive material to be of a first type and the first metal is not capable of significantly doping a semiconductive material;applying the first alloy to a first region of a first surface of the first semiconductor, wherein at least the first region of the first semiconductor has been doped to be a semiconductive material of the first type;heating the first alloy and the first semiconductor above a first temperature point such that at least a portion of the first alloy and a portion of the first semiconductor form a molten second alloy;cooling the second alloy such that at least a portion of the first dopant, contained in the molten second alloy, is incorporated into an expitaxial regrowth region of the first semiconductor such that the regrowth region is doped to a greater concentration than the first region;cooling the second alloy to below the first temperature point wherein the second alloy becomes a solid second contact with ohmic electrical contact to at least a portion of the regrowth region; andwherein the second contact has ohmic electrical contact to the second half.


Solar cells and methods for their manufacture are disclosed. An example solar cell may comprise a substrate comprising a p-type base layer and an n-type selective emitter layer formed over the p-type base layer. The n-type selective emitter layer may comprise one or more first doped regions comprising implanted dopant and one or more second doped regions comprising diffused dopant. The one or more first doped regions may be more heavily doped than the one or more second doped regions. A p-n junction may be formed at the interface of the base layer and the selective emitter layer, such that the p-n junction and the selective emitter layer are both formed during a single anneal cycle.


Patent
Suniva Inc. | Date: 2012-01-09

Solar cells and methods for their manufacture are disclosed. An example method may include providing a substrate comprising a base layer and introducing n-type dopant to the front surface of the base layer by ion implantation. The substrate may be annealed by heating the substrate to a temperature to anneal the implant damage and activate the introduced dopant, thereby forming an n-type doped layer into the front surface of the base layer. Oxygen may be introduced during the annealing step to form a passivating oxide layer on the n-type doped layer. Back contacts may be screen-printed on the back surface of the base layer, and a p-type doped layer may be formed at the interface of the back surface of the base layer and the back contacts during firing of the back contacts. The back contacts may provide an electrical connection to the p-type doped layer.


Patent
Suniva Inc. | Date: 2013-02-28

Back junction solar cells having improved emitter layer coverage and methods for their manufacture are disclosed. In one embodiment, a back junction solar cell includes an n-type base layer having an emitter layer formed from a first p-type doped region (e.g., formed by liquid phase epitaxial regrowth) and a second p-type doped region (e.g., formed by ion implantation) that extends beyond the first region. In various embodiments, this configuration permits the first p-type doped region to be formed with a border between it and the edges of the wafer (e.g., to prevent inadvertent shunting of the cell), while the second p-type doped region extends the emitter layer to improve emitter layer coverage. In certain embodiments, the second doped p-type region may extend to the edges of the wafers n-type base layer.


The invention relates to a solar cell, and to a method of manufacturing a solar cell. The method comprises:forming a first alloy of a first metal and a first dopant, wherein the first dopant is capable of doping a semicondutive material to be of a first type;applying the first alloy to a first surface of a first semiconductor, wherein the first semiconductor has been doped to be a semiconductive material of a second type and the second type is opposite to that of the first type;heating the first alloy and the first semiconductor above a first temperature point such that at least a portion of the first alloy and a portion of the first semiconductor form a molten second alloy;cooling the second alloy such that at least a portion of the first dopant, contained in the molten second alloy, is incorporated into an epitaxial regrowth region of the first semiconductor, wherein at least a portion of the epitaxial regrowth region forms a rectifying junction with the first semiconductor and wherein at least a portion of the rectifying junction is exposable to solar radiation that has not passed through the epitaxial regrowth region;cooling the second alloy to below the first temperature point wherein the second alloy becomes a solid first contact with ohmic electrical contact to at least a portion of the regrowth region; andapplying an ohmic contact to the first semiconductor to form a second electrical contact of the solar cell.


Patent
Suniva Inc. | Date: 2012-03-21

Solar cells, solar modules, and methods for their manufacture are disclosed. An example method may comprise forming a dielectric layer on at least one or more edges of a substrate, and then introducing dopant to at least one surface of the substrate. The substrate may be subjected to a heating process to at least drive the dopant to a predefined depth, thereby forming at least one of an emitter layer and a surface field layer. In the example method, the dielectric layer may not be removed during a subsequent manufacturing process. Associated solar cells and solar modules are also provided.


A thin silicon solar cell is described. An example solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer. A final layer of transparent conductive oxide is formed on both sides Metal contacts are applied to the transparent conductive oxide.


Patent
Suniva Inc. | Date: 2012-09-28

Various embodiments of the present invention are directed to a reduced-area bus bar for collecting current from contacts on the surface of a solar cell. According to various embodiments described herein, a reduced-area bus bar is provided having a width that varies at various points along its longitudinal axis. In particular, the larger width portions of the reduced-area bus bar are configured to provide sufficient pull strength when an interconnecting ribbon is soldered along the bus bar, while the smaller width portions of the reduced-area bus bar enable a reduction in the material required to form the bus bar. Additionally, various embodiments are contemplated in which the reduced-area bus bar comprises a series of segments disposed in a spaced-apart relationship along the bus bars longitudinal axis.


A solar cell comprising:a first region, wherein the first region comprises a homojunction, a top surface, and a bottom surface;a second region coupled to the first region to passivate the top surface of the first region, wherein an interface of the first region and the second region comprises a first heterojunction; anda third region coupled to the first region to passivate the bottom surface of the first region, wherein an interface of the first region and the third region comprises a second heterojunction.


Patent
Suniva Inc. | Date: 2014-05-09

A mounting system for mounting a plurality of solar panels is provided. In one aspect, the mounting system has plurality of panel modules and at least one of: a means for selectively securing a pair of adjacently positioned panel modules to a support structure in an edge-to-edge relationship along a mounting axis that is transverse to the coupling axis, and a means for selectively locking a distal end of one pair of mounting members of one panel module to a proximal end of another pair of mounting members of an adjoining panel module to form at least a portion of one coupled panel module that is adjoined end-to-end along a coupling axis that is transverse to the mounting axis.

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