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Bel Air, MD, United States

Agency: NSF | Branch: Standard Grant | Program: | Phase: | Award Amount: 508.00K | Year: 2011

This Small Business Innovation Research (SBIR) Phase II project will build an FPGA based Bio-informatic appliance for processing DNA sequence data faster, at lower cost and with less power. Over the last decade the cost of sequencing a genome has dropped by six orders of magnitude and the throughput of the process has increased by five orders of magnitude. The trend shows no sign of abating and industry experts expect the $1,000 genome mark to be reached in the next year. The combination of lower prices and higher throughput has lead to what is being called the data deluge or the the data tsunami. Taming this deluge has become a major issue in Bio-informatics and a principle bottleneck to further advances. The objective of this Phase II project is to contribute a solution to the processing problem based on Field Programmable Gate Arrays (FPGAs), non-conventional computing platforms that operate at significantly higher efficiency measured in cost and power per performance unit.

The mechanism of genetic coding, identified by Watson and Crick in 1953, was one of the premier scientific advances of the twentieth century. It took twenty more years to identify a feasible approach to decipher the genetic code of a particular individual and twenty more to actually implement it. The first human genome was sequenced in 2003. By 2010 less than 1,000 humans have been sequenced but rapidly decreasing costs and increasing throughput promise that the number will increase exponentially and medical researchers foresee the day in the near future when the whole population will be sequenced as part of standard medical practice. The advances that will be enabled by partial or full sequencing of the population will bring a revolution to health care ushering in an era of personal genetic based medicine. If successfully deployed, the proposed approach has the potential to address the so-called data deluge and bring about significant savings in both processing time and power consumption.

Stone Ridge Technology | Date: 2012-09-12

Computer hardware and software systems for electronically trading securities.

Agency: National Science Foundation | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 150.00K | Year: 2009

This Small Business Innovation Research (SBIR) Phase I project will investigate the technical and commercial feasibility of a Bioinformatic computing appliance based on FPGA technology. DNA sequencing machines output enormous volumes of raw data with steady year-by-year increases. The initial data processing stages of alignment and mapping are computationally intense and currently present a significant and growing bottleneck. It is believed that an opportunity exists for a new solution that addresses the growing data deluge and computational strain that it introduces. The company proposes to create an appliance using an open-source algorithm for the purpose of a feasibility study. The research objective of the work is to create a powerful and optimized engine for this algorithm that is easily operated by a user through an intuitive web interface. The work will be implemented on a PCI-e based FPGA computing board with two user FPGAs. The application will be optimized to make use of specialized features of the chip. The anticipated result is a Bioinformatic appliance running at 50x to 100x faster than the standard CPU implementation and at lower power and with a smaller physical footprint. The broader impacts of the proposed activity include the potential commercial value and the enhancement of research that will result from wider dissemination of DNA sequencing technology. Full advantages of DNA sequencing are not realized and progress has been slowed by the lack of an efficient and capable processing stage. Traditional solutions using clusters present users with a difficult administration problem. FPGA technology can reduce the size and the power consumption of the data processing stage significantly, making it available to and useful to more companies, labs and health care facilities. The technical and business risk associated with the overall vision of this effort brings with it the possibility of significant commercial impact across the industry.

Agency: Department of Defense | Branch: Air Force | Program: STTR | Phase: Phase I | Award Amount: 100.00K | Year: 2007

The demands of high performance engineering calculations have pushed modern computing architectures based on scalar multiprocessors to their very limits. Larger systems, unstructured grids, multi-scale and multi-phase requirements have all worked to dramatically increase problem complexity. This has created an urgent need for faster, more capable processing techniques. Implementing software algorithms in hardware is one approach to a significant reduction in processing time, however, the specialized nature of custom solutions makes them expensive, inflexible and useful for only the most critical tasks. Field Programmable Gate Arrays (FPGAs) offer the speed of dedicated hardware with the programmable flexibility of software. FPGAs may be inserted into workstations and clusters to provide very effective acceleration. The state of the art suffers from development environments that are ill-suited to general purpose programming and the lack of low cost hardware that is designed to this task. In this project we propose to develop and demonstrate innovative algorithms and computationally effective solutions to problems of engineering physics for the solution of differential equations and the simulation of physics via stochastic techniques.

Gandham R.,Rice University | Esler K.,Stone Ridge Technology | Zhang Y.,Stone Ridge Technology
Computers and Mathematics with Applications | Year: 2014

We present an efficient, robust and fully GPU-accelerated aggregation-based algebraic multigrid preconditioning technique for the solution of large sparse linear systems. These linear systems arise from the discretization of elliptic PDEs. The method involves two stages, setup and solve. In the setup stage, hierarchical coarse grids are constructed through aggregation of the fine grid nodes. These aggregations are obtained using a set of maximal independent nodes from the fine grid nodes. We use a "fine-grain" parallel algorithm for finding a maximal independent set from a graph of strong negative connections. The aggregations are combined with a piece-wise constant (unsmooth) interpolation from the coarse grid solution to the fine grid solution, ensuring low setup and interpolation cost. The grid independent convergence is achieved by using recursive Krylov iterations (K-cycles) in the solve stage. An efficient combination of K-cycles and standard multigrid V-cycles is used as a preconditioner for Krylov iterative solvers such as generalized minimal residual and conjugate gradient. We compare the solver performance with other solvers based on smooth aggregation and classical algebraic multigrid methods. © 2014 Elsevier Ltd. All rights reserved. Source

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