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Pimenta Barros P.,CEA Grenoble | Barnola S.,CEA Grenoble | Gharbi A.,CEA Grenoble | Argoud M.,CEA Grenoble | And 8 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2014

This paper reports on the etch challenges to overcome for the implementation of PS-b-PMMA block copolymer's Directed Self-Assembly (DSA) in CMOS via patterning level. Our process is based on a graphoepitaxy approach, employing an industrial PS-b-PMMA block copolymer (BCP) from Arkema with a cylindrical morphology. The process consists in the following steps: a) DSA of block copolymers inside guiding patterns, b) PMMA removal, c) brush layer opening and finally d) PS pattern transfer into typical MEOL or BEOL stacks. All results presented here have been performed on the DSA Leti's 300mm pilot line. The first etch challenge to overcome for BCP transfer involves in removing all PMMA selectively to PS block. In our process baseline, an acetic acid treatment is carried out to develop PMMA domains. However, this wet development has shown some limitations in terms of resists compatibility and will not be appropriated for lamellar BCPs. That is why we also investigate the possibility to remove PMMA by only dry etching. In this work the potential of a dry PMMA removal by using CO based chemistries is shown and compared to wet development. The advantages and limitations of each approach are reported. The second crucial step is the etching of brush layer (PS-r-PMMA) through a PS mask. We have optimized this step in order to preserve the PS patterns in terms of CD, holes features and film thickness. Several integrations flow with complex stacks are explored for contact shrinking by DSA. A study of CD uniformity has been addressed to evaluate the capabilities of DSA approach after graphoepitaxy and after etching. © 2014 SPIE.


Sukumaran V.,Georgia Institute of Technology | Bandyopadhyay T.,Georgia Institute of Technology | Chen Q.,Georgia Institute of Technology | Kumbhat N.,Georgia Institute of Technology | And 12 more authors.
Proceedings - Electronic Components and Technology Conference | Year: 2011

This paper demonstrates thin glass interposers with fine pitch through package vias (TPV) as a low cost and high I/O substrate for 3D integration. Interposers for packaging of ULK and 3D-ICs need to support large numbers of die to die interconnections with I/O pitch below 50 μm. Current organic substrates are limited by CTE mismatch, wiring density, and poor dimensional stability. Wafer based silicon interposers can achieve high I/Os at fine pitch, but are limited by high cost. Glass is an ideal interposer material due to its insulating property, large panel availability and CTE match to silicon. The main focus of this work is on a) electrical and mechanical design, b) TPV and fine line formation and c) integration process and electrical characterization of thin glass interposers. This work for the first time demonstrates high throughput formation of 30 μm pitch TPVs in ultrathin glass using a parallel laser process. An integration process was demonstrated for glass interposer with polymer build-up layers on both sides. The glass interposer had stable electrical properties up to 20GHz and low insertion loss of less than 0.15dB was measured for TPVs at 9GHz. © 2011 IEEE.


Ronsisvalle C.,STMicrolectronics | Enea V.,STMicrolectronics | Abbate C.,University of Cassino and Southern Lazio | Busatto G.,University of Cassino and Southern Lazio | And 3 more authors.
Proceedings of the International Symposium on Power Semiconductor Devices and ICs | Year: 2011

A new version of a 1200V-20A MOS-GTO with 0.4 cm2 die area is presented. The improvements of the switching performances have been achieved thanks to a new He irradiation technique performed from the back side of the device in order to avoid the degradation of the surface gate oxide. The high energy He irradiation allowed us to kill the lifetime in proximity of the N -/N+ interface in such a way to significantly improve the device switching performances as suggested by the simulations. The irradiation did not affect the on-state characteristics. Instead, a reduction by a factor ∼4 in the storage time and more than 30% decrease in the turn-off energy losses have been measured on irradiated samples with respect to not irradiated ones. © 2011 IEEE.


Balteanu A.,University of Toronto | Sarkas I.,University of Toronto | Adinolfi V.,University of Toronto | Dacquay E.,University of Toronto | And 4 more authors.
IEEE MTT-S International Microwave Symposium Digest | Year: 2012

This paper describes a methodology for extracting the HICUM/L0 model of a 400-GHz SiGe HBT in the presence of strong self-heating. Good agreement is observed between measurements and simulations for DC characteristics, f T, f MAX, and Y parameters in a wide range of frequencies (DC to 170 GHz) and bias conditions. The low power capability of this process is demonstrated in a fundamental frequency 139-150 GHz VCO+161 prescaler consuming less than 99 mW when operated from a L.5V supply. © 2012 IEEE.


Jin Y.,STMicrolectronics | Teysseyre J.,STMicrolectronics | Liu A.R.Y.,STMicrolectronics | Huang B.H.,STMicrolectronics
ECS Transactions | Year: 2013

Fan-out WLP is one of embedded package processed on wafer level, also a key advanced packages with higher number of I/Os, integration flexibilities. Furthermore, it enables to integrate multiple dies vertically and horizontally in one package without using substrates. Thus, recently Fan-out WLP technology is moving forward to next generation packages, such as multi-die, low profile package and 3D SiP. Not only the electronic packages, Fan-out WLP but also is used for sensor, power IC and LED packages This paper reports developments of next generation Fan-out WLP for advanced packaging solutions. Copyright © 2013 by ECS - The Electrochemical Society.


Fiorenza P.,CNR Institute for Microelectronics and Microsystems | Greco G.,CNR Institute for Microelectronics and Microsystems | Iucolano F.,STMicrolectronics | Patti A.,STMicrolectronics | Roccaforte F.,CNR Institute for Microelectronics and Microsystems
Applied Physics Letters | Year: 2015

In this letter, slow and fast trap states in metal-oxide-semiconductor (MOS) capacitors fabricated on recessed AlGaN/GaN heterostructures were studied by frequency dependent conductance measurements. In particular, the comparison of devices before and after annealing in forming gas allowed to ascribe the fast states (with characteristic response time in the range of 5-50 μs) to SiO2/GaN "interface traps," and the slow states (50-100 μs) to "border traps" located few nanometers inside the SiO2 layer. These results can be important to predict and optimize the threshold voltage stability of hybrid MOS-based transistors on GaN. © 2015 AIP Publishing LLC.


Greco G.,CNR Institute for Microelectronics and Microsystems | Iucolano F.,STMicrolectronics | Roccaforte F.,CNR Institute for Microelectronics and Microsystems
Materials Science Forum | Year: 2015

AlGaN/GaN heterostructures are important materials for the fabrication of high power and high frequency devices. However, the mechanisms of Ohmic contacts formation on these systems are continuously under scientific debate. In this paper, a structural and electrical investigation of Ti/Al/Ni/Au Ohmic contacts to AlGaN/GaN heterostructures is reported. In particular, the behavior of Ti/Al/Ni/Au multilayers was monitored at different annealing temperatures. The contacts became Ohmic after annealing at 750°C and showed a decreasing temperature behavior of the specific contact resistance RC, described by a thermionic field emission mechanism. On the other hand, annealing at 850°C led to a further reduction of RC, with a slightly increasing dependence of RC on the measurement temperature (here regarded as a “metal-like” behavior). The microstructural analysis of the interfacial region allowed to explain the results with the formation of metallic intrusions contacting directly the two dimensional electron gas. © (2015) Trans Tech Publications, Switzerland.


Mukherjee A.,TU Dresden | Pawlak A.,TU Dresden | Schroter M.,TU Dresden | Schroter M.,University of California at San Diego | And 2 more authors.
Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 | Year: 2016

An overview on the implementation of new physical effects into the heterojunction bipolar transistor compact model HICUM/L2 is presented along with a description of the quality testing procedures performed before its public release for production circuit design in commercial simulators. Related topics such as potential measures for model run time improvements and failures are also discussed. Significant differences in run time for different commercial circuit simulators reflect their different approaches towards compact model implementation and solution of the non-linear circuit equation system. © 2016 EDAA.


Ronsisvalle C.,STMicrolectronics | Enea V.,STMicrolectronics | Abbate C.,University of Cassino and Southern Lazio | Busatto G.,University of Cassino and Southern Lazio | Sanseverino A.,University of Cassino and Southern Lazio
IEEE Transactions on Electron Devices | Year: 2010

In this brief, we present the experimental and simulated characteristics of a new power semiconductor device called MOS-gated thyristor (MOS-GTO) for high-power applications. The results are presented for a 1.2-kV device and subsequently scaled up to 4.5-kV blocking voltage. The excellent on-state voltage and switching characteristics make MOS-GTO a very promising device for high-voltage power applications. © 2006 IEEE.


Fiorenza P.,CNR Institute for Microelectronics and Microsystems | Frazzetto A.,STMicrolectronics | Guarnera A.,STMicrolectronics | Saggio M.,STMicrolectronics | Roccaforte F.,CNR Institute for Microelectronics and Microsystems
Applied Physics Letters | Year: 2014

The conduction mechanisms and trapping effects at SiO2/4H-SiC interfaces in metal-oxide-semiconductor field effect transistors (MOSFETs) were studied by Fowler-Nordheim (FN) tunnelling and frequency dependent conductance measurements. In particular, the analysis of both MOS capacitors and MOSFETs fabricated on the same wafer revealed an anomalous FN behavior on p-type implanted SiC/SiO2 interfaces. The observed FN instability upon subsequent voltage sweeps was correlated to the charge-discharge of hole trap states close the valence band edge of 4H-SiC. The charge-discharge of these traps also explained the recoverable threshold voltage instability observed in lateral MOSFETs. © 2014 AIP Publishing LLC.

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