STMicroeletronics

Catania, Italy

STMicroeletronics

Catania, Italy

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Fenouillet-Beranger C.,CEA Grenoble | Perreau P.,CEA Grenoble | Boulenc P.,STMicroeletronics | Tosti L.,CEA Grenoble | And 19 more authors.
Solid-State Electronics | Year: 2012

In this paper we explore the impact of the parasitic bipolar in undoped channel Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32 nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The static parasitic bipolar latch occurs at a drain bias superior to the circuit operation alimentation. The several type of ground plane and forward or reverse back biasing do not modify significantly the bipolar breakdown voltage. The thicker EOT gate oxide is more sensible to parasitic bipolar breakdown. Finally, results have been reinforced by using calibrated TCAD simulation tool. © 2012 Elsevier Ltd. All rights reserved.


Fenouillet-Beranger C.,CEA Grenoble | Perreau P.,CEA Grenoble | Benoist T.,CEA Grenoble | Benoist T.,Stendhal University | And 27 more authors.
Solid-State Electronics | Year: 2013

In this paper, we study how to boost the performance of FDSOI (Fully-Depleted Silicon On Insulator) devices with High-K and Single Metal gate by using the combination of Ultra-Thin Buried Oxide (UTBOX), Ground Plane (GP) and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of threshold voltage VT modulation and power management study on the 45 nm 0.374 lm2 bitcells and on the ESD functionality as compared to bulk technology. © 2013 Elsevier Ltd. All rights reserved.


Fenouillet-Beranger C.,CEA Grenoble | Perreau P.,CEA Grenoble | Denorme S.,STMicroeletronics | Tosti L.,CEA Grenoble | And 29 more authors.
Solid-State Electronics | Year: 2010

In this paper we explore for the first time the impact of an ultra-thin BOX (UTBOX) with and without ground plane (GP) on a 32 nm fully-depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50 mV DIBL reduction by using 10 nm BOX thickness for NMOS and PMOS devices at 33 nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299μm2 SRAM cell while maintaining an SNM of 296 mV@Vdd 1.1 V. © 2010 Elsevier Ltd.


Gentile A.,University of Catania | Gentile A.,CNR Institute for Microelectronics and Microsystems | Cacciato G.,University of Catania | Cacciato G.,CNR Institute for Microelectronics and Microsystems | And 11 more authors.
Journal of Materials Science | Year: 2014

In this work, we propose a methodology to synthesize metallic nanoparticles on textured Fluorine Tin Oxide (FTO) surface by laser irradiations of deposited Au films. In particular, the breakup of the Au films into nanoparticles (NPs) is observed as a consequence of the melting and solidification processes induced by laser irradiations. The mean Au NPs size and surface density evolution are analyzed as a function of the laser fluence. Optical characterizations of the glass/FTO/Au NPs multilayer show, in the absorption spectra, plasmonic peaks due to the Au NPs and an improvement of the light absorption efficiency from the sample with larger Au NPs. The simulated trends of the ratio between the scattering and absorption cross section suggest that the absorption efficiency dominates over the scattering efficiency in the spectral range between 200 and 600 nm. The simulation shows that, by varying the NPs radius from about 18 to 24 nm, the radiation-scattered intensity remains symmetric in forward and reverse directions. These results indicate that the surface coverage size distribution of Au NPs is the key parameter to correlate the structural and optical properties of the glass/FTO/Au NPs multilayer. Furthermore, electrical characterizations highlight a reduction in the sheet resistance of the textured FTO due to the presence of the NPs. We compare these results with those obtained for the same systems when standard furnace annealing processes are used to obtain the Au NPs on the textured FTO surface. © Springer Science+Business Media New York 2014.


Koton J.,Brno University of Technology | Lahiri A.,STMicroeletronics | Herencsar N.,Brno University of Technology | Vrba K.,Brno University of Technology
2011 34th International Conference on Telecommunications and Signal Processing, TSP 2011 - Proceedings | Year: 2011

In this paper a fully CMOS implementation of current-mode full-wave precision rectifier is presented. The structure is generally based on the recently presented Lazzaro's winner-takes-all (WTA) circuit. The rectifier has been implemented using the 0.35 m CMOS technology and its behavior verified by SPICE. The simulation results shown feasibility to process signals of frequencies up to 20 MHz. © 2011 IEEE.


Gentile A.,University of Catania | Gentile A.,CNR Institute for Microelectronics and Microsystems | Cacciato G.,University of Catania | Cacciato G.,CNR Institute for Microelectronics and Microsystems | And 14 more authors.
Functional Materials Letters | Year: 2015

We report about the modulation of the electrical properties of thin film solar cells due to the incorporation of size-selected Au nanostructures (NSs) at a textured FTO/p-i-n interface. By increasing the Au NSs size, the analyses of current-voltage characteristics show lower Schottky barrier heights and the gradual reduction of the open-circuit voltages (VOC). The optical measurements show higher parasitic absorption by larger Au NSs that reduces the amount of radiation transmitted by the transparent to absorber layer. This process decreases the number of photo-generated carriers and may explain the VOC reduction related to the devices with larger Au NSs at the interface. So, the correlation between materials properties and device performances was established. © 2015 World Scientific Publishing Company.


Le Maitre P.,STMicroeletronics | Carpentier J.-F.,STMicroeletronics | Baudot C.,STMicroeletronics | Vulliet N.,STMicroeletronics | And 4 more authors.
European Conference on Optical Communication, ECOC | Year: 2015

We study the process variability impact of silicon ring modulators on resonance wavelength, which is a key parameter to design WDM communication systems based on those devices. © 2015 Viajes el Corte Ingles, VECISA.


Gentile A.,University of Catania | Gentile A.,CNR Institute for Microelectronics and Microsystems | Cacciato G.,University of Catania | Cacciato G.,CNR Institute for Microelectronics and Microsystems | And 13 more authors.
Journal of Materials Science | Year: 2014

In this work, we propose a methodology to synthesize metallic nanoparticles on textured Fluorine Tin Oxide (FTO) surface by laser irradiations of deposited Au films. In particular, the breakup of the Au films into nanoparticles (NPs) is observed as a consequence of the melting and solidification processes induced by laser irradiations. The mean Au NPs size and surface density evolution are analyzed as a function of the laser fluence. Optical characterizations of the glass/FTO/Au NPs multilayer show, in the absorption spectra, plasmonic peaks due to the Au NPs and an improvement of the light absorption efficiency from the sample with larger Au NPs. The simulated trends of the ratio between the scattering and absorption cross section suggest that the absorption efficiency dominates over the scattering efficiency in the spectral range between 200 and 600 nm. The simulation shows that, by varying the NPs radius from about 18 to 24 nm, the radiation-scattered intensity remains symmetric in forward and reverse directions. These results indicate that the surface coverage size distribution of Au NPs is the key parameter to correlate the structural and optical properties of the glass/FTO/Au NPs multilayer. Furthermore, electrical characterizations highlight a reduction in the sheet resistance of the textured FTO due to the presence of the NPs. We compare these results with those obtained for the same systems when standard furnace annealing processes are used to obtain the Au NPs on the textured FTO surface. © 2014 Springer Science+Business Media New York.


Bouzid S.,Laboratory for Information science and Systems | Cauvet C.,Laboratory for Information science and Systems | Pinaton J.,STMicroeletronics
Proceedings - 2012 International Conference on Information Retrieval and Knowledge Management, CAMP'12 | Year: 2012

With the increase of information resources and software assets in industries, many companies seek today to improve knowledge sharing and the access to information. In fact, information retrieval has become a daily challenge for many actors of these companies where the quantity of information is huge and is from different sources. The semantic web field tries to address this problem by offering many techniques to attach semantic annotations to resources using the ontology of a given domain. This paper presents a survey of semantic web standards which aim at representing knowledge for many contexts of application. Our goal is to choose the most appropriate standard for representing knowledge in the context of problem solving. © 2012 IEEE.


Drouin D.,LN2 Laboratoire Nanotechnologies Nanosystemes | Droulers G.,LN2 Laboratoire Nanotechnologies Nanosystemes | Labalette M.,LN2 Laboratoire Nanotechnologies Nanosystemes | Sang B.L.,LN2 Laboratoire Nanotechnologies Nanosystemes | And 10 more authors.
IEEE-NANO 2015 - 15th International Conference on Nanotechnology | Year: 2015

In this paper we present a versatile nanodamascene fabrication process for the realization of low power nanoelectronic devices. This process has been exploited for the fabrication of metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar nanometric resistive memories. Due to its low thermal budget, and materials, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration. © 2015 IEEE.

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