Geneva, Switzerland

STMicroelectronics

www.st.com/
Geneva, Switzerland

STMicroelectronics is a French-Italian electronics and semiconductor manufacturer headquartered in Geneva, Switzerland. While STMicroelectronics corporate headquarters and the headquarters for EMEA region are based in Geneva, the holding company, STMicroelectronics N.V. is registered in Amsterdam, Netherlands. The company’s US headquarters is in Coppell, Texas. Headquarters for the Asia-Pacific region is in Singapore whilst Japan and Korea operations are headquartered in Tokyo. Wikipedia.


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An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.


A semiconductor device includes a quadrilateral package with a first pair of opposed sides and a second pair of opposed sides. Both sides of the first pair of opposed sides are provided with electrical contact leads. Only one side of the second pair of opposed sides is provided with electrical contact leads. The side of the second pair of opposed sides without electrical contact leads is a leadless side. That side is not a molded side of the package, but rather is defined by a cut surface.


Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.


Patent
Ibm and STMicroelectronics | Date: 2017-02-03

The present disclosure is directed to fluid filtering systems and methods for use during semiconductor processing. One or more embodiments are directed to fluid filtering systems and methods for filtering ions and particles from a fluid as the fluid is being provided to a semiconductor wafer processing tool, such as to a semiconductor wafer cleaning tool.


Patent
STMicroelectronics | Date: 2017-01-10

The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.


A vacuum integrated electronic device (120) has an anode region (101) of conductive material; an insulating region (102, 104) on top of the anode region; a cavity (54) extending through the insulating region and having a sidewall (53); and a cathode region (109). The cathode region has a tip portion (51, 52) extending peripherally within the cavity, adjacent to the sidewall of the cavity. The cathode region is formed by tilted deposition, carried out at an angle of 30-60 with respect to a perpendicular to the surface of device.


Method for production of a semiconductor wafer suitable for the manufacture of an SOI substrate, comprising the following steps: - production, on the upper face (2) of a semiconductor support (1), of a first layer (4) of polycrystalline semiconductor; then - formation of an interface area (12) on the upper face (7) of said first layer (4), the interface area (12) having a structure distinct from the crystalline structure of said first layer (4); then - production on said interface area (12) of a second layer (14) of polycrystalline semiconductor.


Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.


Patent
STMicroelectronics | Date: 2017-02-08

An integrated-circuit card (1) is described, said card comprising a substrate (2) and a circuit (3) integrated in the substrate (2), with the pads of the circuit (3) substantially coplanar with a surface (S) of the substrate (2). The substrate (2) comprises a first area defining a first sector (5) comprising the circuit (3) and able to be separated from the card (1), said first sector (5) having a form and size equivalent to a 4FF format of integrated-circuit cards and being intended to be separated from the card owing to a first pre-cut or weakening line (4) delimiting said first sector (5) with 4FF format; the card further comprises at least one area defining a second sector (7) around the first sector (5) and able to be separated from card (1) owing to a second pre-cut or weakening line (6), said second sector (7) having a form or size equivalent to a 2FF or 3FF format of integrated-circuit cards, and a screen-printed coating (8) on the surface (SC) opposite to the surface (S) of the substrate (2), in the region of at least the second sector (7), the screen-printed coating (8) having, along the second sector (7), a thickness (B) which is equal to the difference between a predefined thickness (X) of the 2FF or 3FF format and a thickness (A) of the first sector ( 5 ).


Patent
STMicroelectronics | Date: 2017-07-12

A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.

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